參數(shù)資料
型號(hào)： LAN83C185-JT
廠(chǎng)商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 12/61頁(yè)
文件大小： 459K
代理商： LAN83C185-JT
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Rev. 0.8 (11-16-04)
12
SMSC LAN83C185
DATASHEET
Chapter 3 Pin Description
This chapter describes in detail the functionality of each of the five main architectural blocks.
The term “block” defines a stand-alone entity on the floor plan of the chip.
3.1
I/O Signals
I
– Input. Digital TTL levels.
O
– Output. Digital TTL levels.
AI
– Input. Analog levels.
AO
– Output. Analog levels.
AI/O – Input or Output. Analog levels.
Note:
Reset as used in the signal descriptions is defined as nRST being active low.
Configuration inputs are listed in parenthesis.
Table 3.1 MII Signals
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
41
TXD0
I
Transmit Data 0
: Bit 0 of the 4 data bits that are accepted
by the PHY for transmission.
42
TXD1
I
Transmit Data 1
: Bit 1 of the 4 data bits that are accepted
by the PHY for transmission.
39
TX_EN
I
Transmit Enable
: Indicates that valid data is presented
on the TXD[3:0] signals, for transmission.
35
RX_ER
(RXD4)
O
O
Receive Error
: Asserted to indicate that an error was
detected somewhere in the frame presently being
transferred from the PHY.
In Symbol Interface (5B Decoding) mode, this signal is the
MII Receive Data 4
: the MSB of the received 5-bit symbol
code-group.
47
COL
O
MII Collision Detect
: Asserted to indicate detection of
collision condition.
32
RXD0
O
Receive Data 0
: Bit 0 of the 4 data bits that are sent by
the PHY in the receive path.
31
RXD1
O
Receive Data 1
: Bit 1 of the 4 data bits that are sent by
the PHY in the receive path.
44
TXD2
I
Transmit Data 2
: Bit 2 of the 4 data bits that are accepted
by the PHY for transmission.
45
TXD3
I
Transmit Data 3
:
Bit 3 of the 4 data bits that are accepted
by the PHY for transmission.
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