參數(shù)資料
型號(hào)： LAN83C185-JT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64
文件頁(yè)數(shù)： 40/61頁(yè)
文件大?。?/td> 459K
代理商： LAN83C185-JT
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Rev. 0.8 (11-16-04)
40
SMSC LAN83C185
DATASHEET
18.4:0
PHYAD
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to
Section 5.4.9.1, "Physical Address Bus -
PHYAD[4:0]," on page 46
for more details.
RW,
NASR
PHYAD
Table 5.44 Register 20 - TSTCNTL
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
20.15
READ
When setting this bit to “1”, the content of the register
that is selected by the READ ADDRESS will be
latched to the TSTREAD1/2 registers. This bit is self-
cleared.
RW
0
20.14
WRITE
When setting this bit to “1”, the register that is selected
by the WRITE ADDRESS is going to be written with
the data from the TSTWRITE register. This bit is self-
cleared.
RW
0
20.13:11
Reserved
20.10
TEST MODE
Enable the Testability/Configuration mode:
0 - Testability/Configuration mode disabled
1 - Testability/Configuration mode enabled
RW
0
20.9:5
READ
ADDRESS
The address of the Testability/Configuration register
that will be latched into the TSTREAD1 and
TSTREAD2 registers
RW
0
20.4:0
WRITE
ADDRESS
The address of the Testability/Configuration register
that will be written.
RW
0
Table 5.45 Register 21 - TSTREAD1
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
21.15:0
READ_DATA
When reading registers with a size of less then 16
bits, this register contain the register data, starting
from bit 0.
When reading registers with a size of more then 16
bits, this register contain the less significant 16 bits of
the register data.
RO
0
Table 5.46 Register 22 - TSTREAD2
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
22.15:0
READ_DATA
When reading registers with a size of less then 16
bits, this register clears to zeros.
When reading registers with a size of more then 16
bits, this register contains the most significant bits of
the register data, starting from the 16
th
bit.
RO
0
Table 5.43 Register 18 - Special Modes (continued)
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
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