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參數(shù)資料
| 型號： | LAN83C185-JT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 27/61頁 |
| 文件大?。?/td> | 459K |
| 代理商： | LAN83C185-JT |
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
27
Rev. 0.8 (11-16-04)
DATASHEET
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in
Figure 4.4
and
Figure 4.5
.
The timing relationships of the MDIO signals are further described in
Section 6.1, "Serial
Management Interface (SMI) Timing," on page 51
.
Figure 4.4 MDIO Timing and Frame Structure - READ Cycle
Figure 4.5 MDIO Timing and Frame Structure - WRITE Cycle
MDC
MDI0
Read Cycle
...
...
32 1's
0
1
1
0
A4
A3
A2
A1
A0
R4
R3
R2
R1
R0
D1
D15
D14
D0
Preamble
Start of
Frame
OP
Code
PHY Address
Register Address
Turn
Around
Data
Data From Phy
Data To Phy
MDC
MDIO
...
32 1's
0
1
1
0
A4
A3
A2
A1
A0
R4
R3
R2
R1
R0
Write Cycle
D15
D14
D1
D0
...
Data
Preamble
Start of
Frame
OP
Code
PHY Address
Register Address
Turn
Around
Data To Phy
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