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參數(shù)資料
| 型號： | LAN83C185-JT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 34/61頁 |
| 文件大?。?/td> | 459K |
| 代理商： | LAN83C185-JT |
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Rev. 0.8 (11-16-04)
34
SMSC LAN83C185
DATASHEET
5.1
SMI Register Mapping
The following registers are supported (register numbers are in decimal):
5.2
SMI Register Format
The mode key is as follows:
■
RW = read/write,
■
SC = self clearing,
■
WO = write only,
■
RO = read only,
■
LH = latch high, clear on read of register,
■
LL = latch low, clear on read of register,
■
NASR = Not Affected by Software Reset
Table 5.33 SMI Register Mapping
REGISTER #
DESCRIPTION
GROUP
0
Basic Control Register
Basic
1
Basic Status Register
Basic
2
PHY Identifier 1
Extended
3
PHY Identifier 2
Extended
4
Auto-Negotiation Advertisement Register
Extended
5
Auto-Negotiation Link Partner Ability Register
Extended
6
Auto-Negotiation Expansion Register
Extended
16
Silicon Revision Register
Vendor-specific
17
Mode Control/Status Register
Vendor-specific
18
Special Modes
Vendor-specific
20
TSTCNTL – Testability/Configuration Control
Vendor-specific
21
TSTREAD1 – Testability data Read for LSB
Vendor-specific
22
TSTREAD2 – Testability data Read for MSB
Vendor-specific
23
TSTWRITE – Testability/Configuration data Write
Vendor-specific
27
Control / Status Indication Register
Vendor-specific
28
Special internal testability controls
Vendor-specific
29
Interrupt Source Register
Vendor-specific
30
Interrupt Mask Register
Vendor-specific
31
PHY Special Control/Status Register
Vendor-specific
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