參數(shù)資料
型號: K4S160822D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL
中文描述: 2Mx8 SDRAM的1M × 8位× 2銀行同步DRAM LVTTL
文件頁數(shù): 44/46頁
文件大?。?/td> 1183K
代理商: K4S160822D
KM48S2120D
CMOS SDRAM
- 44
Rev.1.0 (Mar. 1999)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Self Refresh Entry & Exit Cycle
Self Refresh Entry
: Don't care
*Note 1
*Note 7
Hi-Z
Hi-Z
Self Refresh Exit
Auto Refresh
tSS
*Note 2
*Note 3
*Note 4
tRCmin
*Note 6
*Note 5
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A
10
/AP
*Note :
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays
"Low".
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
相關(guān)PDF資料
PDF描述
K4S161622D 512K x 16Bit x 2 Banks Synchronous DRAM
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K4S161622E-TC60 1M x 16 SDRAM
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