參數(shù)資料
型號： JS28F128P30T85
廠商： INTEL CORP
元件分類： DRAM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 8M X 16 FLASH 1.8V PROM, 85 ns, PDSO56
封裝： 14 X 20 MM, LEAD FREE, TSOP-56
文件頁數(shù)： 83/102頁
文件大?。?/td> 1609K
代理商： JS28F128P30T85
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
83
Notes:
1.
"Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase],
etc.)
If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at
different locations in the address map.
1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will
occur.
To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle
command sequence in which the second cycle will be ignored. For example, when the device is program suspended and
an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be
ignored because it is unclear whether the user intends to erase the block or resume the program operation.
2.
3.
4.
Figure 39.
Write State Machine—Next State Table (Sheet 6 of 6)
OTP Busy
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Suspend
BEFP Setup,
BEFP Pgm & Verify
Busy,
Erase Setup,
OTP Setup,
BP:
Setup
, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Current chip state
Ready,
Erase Suspend,
BP Suspend
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
OTP
Setup
(4)
Lock
Block
Confirm
(8)
Lock-Down
Block
Confirm
(8)
Write CR
Confirm
(8)
Block Address
(WA0)
Illegal Cmds or
BEFP Data
(1)
(C0H)
(01H)
(2FH)
(03H)
(FFFFH)
(all other codes)
WSM
Operation
Completes
Output does
not change.
Array
Read
Status Read
Array Read
Output does not
change.
Output does not change.
Status
Read
Status Read
Status Read
Command Input to Chip and resulting
Output
Mux Next State
Output
Next State Table
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