參數(shù)資料
型號(hào): ISP1582
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設(shè)控制器
文件頁(yè)數(shù): 46/66頁(yè)
文件大小: 325K
代理商: ISP1582
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
46 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (2Ch) at any time. Doing so would result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If
the DMA Endpoint register, however, is pointed to an active endpoint, the firmware
must not reference the same endpoint on the Endpoint Index register.
9.4.8
DMA Burst Counter register (address: 64h)
Table 63
shows the bit allocation of the register.
9.5 General registers
9.5.1
Interrupt register (address: 18h)
The Interrupt register consists of 4 bytes. The bit allocation is given in
Table 65
.
Table 62:
Bit
7 to 4
3 to 1
0
DMA Endpoint register: bit description
Symbol
Description
-
reserved
EPIDX[2:0]
selects the indicated endpoint for DMA access
DMADIR
0 —
Selects the RX/OUT FIFO for DMA read transfers
1 —
Selects the TX/IN FIFO for DMA write transfers.
Table 63:
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Burst Counter register: bit allocation
15
14
reserved
-
-
-
-
-
-
7
6
13
12
11
10
9
8
BURSTCOUNTER[12:8]
0
0
R/W
R/W
3
-
-
-
5
0
0
0
0
0
0
0
0
R/W
4
R/W
1
R/W
0
2
BURSTCOUNTER[7:0]
0
0
R/W
0
0
0
0
0
0
0
0
0
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 64:
Bit
15 to 13 -
12 to 0
DMA Burst Counter register: bit description
Symbol
Description
reserved
This register defines the burst length. The counter must
be programmed to be a multiple of two in 16-bit mode.
The value of the burst counter should be programmed
such that the buffer counter is a factor of the burst
counter.
BURSTCOUNTER[12:0]
For IN endpoint —
When the burst counter equals 2,
in GDMA mode, DREQ will drop at every DMA read or
write cycle.
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