參數(shù)資料
型號(hào): ISP1582
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線(xiàn)外設(shè)控制器
文件頁(yè)數(shù): 39/66頁(yè)
文件大?。?/td> 325K
代理商: ISP1582
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
39 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
interrupt is generated by the ISP1582. If the DMA master wishes to terminate the
DMA transfer, it can issue an EOT signal to the ISP1582. This EOT signal overrides
the transfer counter and can terminate the DMA transfer at any time.
In EOT-only mode, DIS_XFER_CNT has to be set to logic 1. Although the DMA
transfer counter can still be programmed, it will not have any effect on the DMA
transfer. The DMA transfer will start once the DMA command is issued. Any of the
following three ways will terminate this DMA transfer:
Detecting an external EOT
Detecting an internal EOT (short packet on an OUT token)
Resetting the DMA.
There are three interrupts programmable to differentiate the method of DMA
termination: bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt
Reason register. For details, see
Table 58
.
Remark:
The DMA bus defaults to three-state, until a DMA command is executed. All
the other control signals are not three-state.
9.4.1
DMA Command register (address: 30h)
The DMA Command register is a 1-byte register (for bit allocation, see
Table 47
) that
initiates all DMA transfer activity on the DMA controller. The register is write-only:
reading it will return FFh.
Remark:
The DMA bus will be in three-state until a DMA command is executed.
Table 46:
Control bits
DMA Configuration register
MODE[1:0]
WIDTH
DIS_XFER_CNT
DMA Hardware register
EOT_POL
ENDIAN[1:0]
Control bits for GDMA read/write (opcode = 00h/01h)
Description
Reference
Determines the active read/write data strobe signals.
Selects the DMA bus width: 8 or 16 bits.
Disables the use of the DMA Transfer Counter.
Table 52
Selects the polarity of the EOT signal.
Determines whether the data is to be byte swapped or
normal. Applicable only in 16-bit mode.
Select the polarity of the DMA handshake signals.
Table 54
ACK_POL,
DREQ_POL,
WRITE_POL,
READ_POL
Table 47:
Bit
Symbol
Reset
Bus reset
Access
DMA Command register: bit allocation
7
6
5
4
DMA_CMD[7:0]
1
1
W
3
2
1
0
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
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