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參數(shù)資料
| 型號： | ISP1582 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral controller |
| 中文描述： | 高速通用串行總線外設控制器 |
| 文件頁數(shù)： | 38/66頁 |
| 文件大小： | 325K |
| 代理商： | ISP1582 |
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Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
38 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4 DMA registers
The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the
DMA Command register. The control bits are given in
Table 46
.
GDMA read/write (opcode = 00h/01h) for Generic DMA slave mode
Depending on the MODE[1:0] bit set in the DMA configuration register, either the
DACK signal or the DIOR/DIOW signals strobe the data. These signals are driven by
the external DMA controller.
GDMA (slave) mode can operate in either counter mode or EOT-only mode.
In counter mode, bit DIS_XFER_CNT in the DMA Configuration register must be set
to logic 0. The DMA Transfer Counter register must be programmed before any DMA
command is issued. The DMA transfer counter is set by writing from the LSByte to the
MSByte (address: 34h to 37h). The DMA transfer count is internally updated only
after the MSByte has been written. Once the DMA transfer is started, the transfer
counter starts decrementing and on reaching 0, bit DMA_XFER_OK is set and an
Bit
Symbol
Reset
Bus reset
Access
7
6
5
4
3
2
1
0
reserved
-
-
R/W
NOEMPKT
0
0
R/W
ENABLE
0
0
R/W
DBLBUF
0
0
R/W
ENDPTYP[1:0]
0
0
R/W
-
-
-
-
0
0
R/W
R/W
R/W
Table 45:
Bit
15 to 5
4
Endpoint Type register: bit description
Symbol
Description
-
reserved
NOEMPKT
No Empty Packet:
Logic 0 causes the ISP1582 to return a null
length packet for the IN token after the DMA IN transfer is
complete. For ATA mode or the IN DMA transfer, which does not
require a null length packet after DMA completion, set to logic 1 to
disable the generation of the null length packet.
ENABLE
Endpoint Enable
: Logic 1 enables the FIFO of the indexed
endpoint. The memory size is allocated as specified in the
Endpoint MaxPacketSize register. Logic 0 disables the FIFO.
Remark:
‘Stall’ing a data endpoint will confuse the Data Toggle bit
on the stalled endpoint because the internal logic picks up from
where it has stalled. Therefore, the Data Toggle bit must be reset
by disabling and reenabling the corresponding endpoint (by setting
bit ENABLE to logic 0 or logic 1 in the Endpoint Type register) to
reset the PID.
DBLBUF
Double Buffering:
Logic 1 enables double buffering for the
indexed endpoint. Logic 0 disables double buffering.
ENDPTYP[1:0]
Endpoint Type:
These bits select the endpoint type as follows.
3
2
1 to 0
00 —
not used
01 —
Isochronous
10 —
Bulk
11 —
Interrupt.
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相關代理商/技術參數(shù) |
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|---|---|
| ISP1582 PCI EVALKIT | 功能描述:PCI BUS EVAL KIT ISP1582 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| ISP1582BS | 功能描述:IC USB CTRL HI-SPEED 56HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1582BS,518 | 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BS,551 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BS,557 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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