參數(shù)資料
型號(hào)： ISP1582
廠商： NXP Semiconductors N.V.
英文描述： Hi-Speed Universal Serial Bus peripheral controller
中文描述： 高速通用串行總線外設(shè)控制器
文件頁(yè)數(shù)： 33/66頁(yè)
文件大?。?/td> 325K
代理商： ISP1582
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
33 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.3.2
Control Function register (address: 28h)
The Control Function register performs the buffer management on endpoints. It
consists of 1 byte, and the bit configuration is given in
Table 33
. The register bits can
stall, clear or validate any enabled data endpoint. Before accessing this register, the
Endpoint Index register must be written first to specify the target endpoint.
9.3.3
Data Port register (address: 20h)
This 2-byte register provides direct access for a microcontroller to the FIFO of the
indexed endpoint. The bit allocation is shown in
Table 35
.
Table 33:
Bit
Symbol
Reset
Bus reset
Access
Control Function register: bit allocation
7
reserved
-
-
R/W
R/W
6
5
4
3
2
1
0
CLBUF
0
0
R/W
VENDP
0
0
R/W
DSEN
0
0
R/W
STATUS
0
0
R/W
STALL
0
0
R/W
-
-
-
-
R/W
Table 34:
Bit
7 to 5
4
Control Function register: bit description
Symbol
Description
-
reserved
CLBUF
Clear Buffer:
Logic 1 clears the RX buffer of the indexed endpoint; the TX
buffer is not affected. The RX buffer is automatically cleared once the
endpoint is completely read. This bit is set only when it is necessary to
forcefully clear the buffer.
VENDP
Validate Endpoint:
Logic 1 validates the data in the TX FIFO of an IN
endpoint for sending on the next IN token. In general, the endpoint is
automatically validated when its FIFO byte count has reached the
endpoint MaxPacketSize. This bit is set only when it is necessary to
validate the endpoint with the FIFO byte count which is below the
Endpoint MaxPacketSize.
DSEN
Data Stage Enable
: This bit controls the response of the ISP1582 to a
control transfer. When this bit is set, the ISP1582 goes to the data stage;
otherwise, the ISP1582 will NAK the data stage transfer until the firmware
explicitly responds to the setup command.
STATUS
Status Acknowledge:
Only applicable for control IN/OUT.
This bit controls the generation of ACK or NAK during the status stage of
a SETUP transfer. It is automatically cleared when the status stage is
completed, or when a SETUP token is received. No interrupt signal will be
generated.
3
2
1
0 —
Sends NAK
1 —
Sends an empty packet following the IN token (host-to-peripheral) or
ACK following the OUT token (peripheral-to-host).
Stall Endpoint
: Logic 1 stalls the indexed endpoint. This bit is not
applicable for isochronous transfers.
Remark:
‘Stall’ing a data endpoint will confuse the Data Toggle bit about
the stalled endpoint because the internal logic picks up from where it is
stalled. Therefore, the Data Toggle bit must be reset by disabling and
reenabling the corresponding endpoint (by setting bit ENABLE to logic 0
or logic 1 in the Endpoint Type register) to reset the PID.
0
STALL
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ISP1582BS,551 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1582BS,557 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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