參數(shù)資料
型號: ISP1582
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設控制器
文件頁數(shù): 15/66頁
文件大?。?/td> 325K
代理商: ISP1582
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
15 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.11.2
Interrupt control
Bit GLINTENA in the Mode register is a global enable/disable bit. The behavior of this
bit is given in
Figure 5
.
Event A: When an interrupt event occurs (for example, SOF interrupt) with
bit GLINTENA set to logic 0, an interrupt will not be generated at pin INT. It will,
however, be registered in the corresponding Interrupt register bit.
Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in
the Interrupt register is already set.
Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted.
The bold dashed line shows the desired behavior of pin INT.
Deassertion of pin INT can be achieved either by clearing all the Interrupt register or
the DMA Interrupt Reason register, depending on the event.
Remark:
When clearing an interrupt event, perform write to all the bytes of the
register.
For more information on interrupt control, see
Section 9.2.2
,
Section 9.2.5
and
Section 9.5.1
.
8.12 V
BUS
sensing
Pin V
BUS
is one of the ways to wake up the clock when the ISP1582 is suspended
with bit CLKAON set to logic 0 (clock off option).
To detect whether the host is connected or not, that is V
BUS
sensing, a 1 M
resistor
and a 1
μ
F electrolytic capacitor must be added to damp the overshoot upon plug-in.
Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled).
Fig 5.
Behavior of bit GLINTENA.
INT pin
004aaa394
GLINTENA = 0
SOF asserted
GLINTENA = 1
SOF asserted
GLINTENA = 0
(during this time,
an interrupt event
occurs. For example,
SOF asserted.)
A
B
C
Fig 6.
Resistor and electrolytic capacitor needed for V
BUS
sensing.
1 M
ISP1582
004aaa440
+
1 μF
49
USB
Connector
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