參數(shù)資料
型號(hào): ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 85/102頁
文件大小: 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
85 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
8
PR
Port Reset
: logic 1 means the Port is in Reset. A logic 0 means
the Port is not in Reset. Default = 0. When software sets this bit (from
a logic 0), the bus reset sequence as defined in the Universal Serial
Bus Specification Rev. 2.0is started. Software clears this bit to
terminate the bus reset sequence. Software must hold this bit at
logic 1 until the reset sequence, as specified in the Universal Serial
Bus Specification Rev. 2.0 is completed.
Remark:
When software sets this bit, it must also clear the Port
Enable bit.
Remark:
When software clears this bit, there may be a delay before
the bit status changes to logic 0, because it will not read Logic 0 until
the reset is completed. If the port is in the high-speed mode after reset
is completed, the Host Controller will automatically enable this port (it
can set the Port Enable bit). A Host Controller must terminate the
reset and stabilize the state of the port within 2 ms of software
changing this bit from a logic 1 to a logic 0. For example, if the port
detects that the attached device is high-speed during a reset, then the
Host Controller must enable the port within 2 ms of software clearing
this bit.
The HCH (HCHalted) bit in the USBSTS register must be a logic 0
before software attempts to use this bit. The Host Controller may hold
Port Reset asserted when the HCH (HCHalted) bit is set.
[1]
Suspend
: Default = 0. A logic 1 means the Port is in the suspend
state. A logic 0 means the Port is not suspended. The Port Enabled bit
and the Suspend bit of this register define the port states as follows:
7
SUSP
PED = 0 and SUSP = x —
port is disabled
PED = 1 and SUSP = 0 —
port is enabled
PED = 1 and SUSP = 1 —
port is suspended
When in the suspend state, downstream propagation of data is
blocked on this port, except for the port reset. If a transaction was in
progress when this bit was set, he blocking occurs at the end of the
current transaction. In the suspend state, the port is sensitive to
resume detection. Note that the bit status does not change until the
port is suspended and that there may be a delay in suspending a port
if there is a transaction currently in progress on the USB. Attempts to
clear this bit are ignored by the Host Controller. The Host Controller
will unconditionally set this bit to a logic 0 when:
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
If the host software sets this bit when the Port Enabled bit is a logic 0,
the results are undefined.
[1]
Table 117: PORTSC 1, 2, 3, 4 register: bit description
…continued
Bit
Symbol
Description
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