參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 84/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
84 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
13
PO
Port Owner
: Default = 1. This bit unconditionally goes to a 0 when the
Configured bit in the CONFIGFLAG register makes a 0 to 1 transition.
This bit unconditionally goes to 1 whenever the Configured bit is zero.
System software uses this field to release ownership of the port to a
selected Host Controller (in the event that the attached device is not a
high-speed device). Software writes a one to this bit when the
attached device is not a high-speed device. A one in this bit means
that a companion Host Controller owns and controls the port.
Port Power
: The function of this bit depends on the value of the Port
Power Control (PPC) field in the HCSPARAMS register.
12
PP
If PPC = 0 and PP = 1 —
The Host Controller does not have port
power control switches. Each port is hardwired to power.
If PPC = 1 and PP = 1 or 0 —
The Host Controller has port power
control switches. This bit represents the current setting of the switch
(logic 0 = OFF, logic 1 = ON). When PP is logic 0, the port is
non-functional and will not report any status
When an overcurrent condition is detected on a powered port and
PPC is a logic 1, the PP bit in each affected port may be changed by
the Host Controller from a logic 1 to a logic 0 (removing power from
the port).
Line Status
: This field reflect the current logical levels of the DP
(bit 11) and DM (bit 10) signal lines. These bits are used for detection
of low-speed USB devices prior to the port reset and enable
sequence. This field is valid only when the Port Enable bit is zero and
the current connect status bit is set to one.
11 to 10
LS[1:0]
00B —
SE0: Not low-speed device, perform EHCI reset
01B —
J-state: Not low-speed device, perform EHCI reset
10B —
K-state: Low-speed device, release ownership of port
11B —
undefined: Not low-speed device, perform EHCI reset.
If Port Power (PP) is zero, this field is undefined.
reserved
9
-
Table 117: PORTSC 1, 2, 3, 4 register: bit description
…continued
Bit
Symbol
Description
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