參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 51/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
51 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.1.13
HcDoneHead register (address: value read from func0 or func1 of address
10H
+
30H)
The HcDoneHead register contains the physical address of the last completed TD
that was added to the Done queue. In normal operation, the HCD does not need to
read this register as its content is periodically written to the HCCA.
Table 66
contains
the bit allocation of the register.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15
14
13
12
11
10
9
8
BCED[11:4]
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
BCED[3:0]
reserved
0
0
0
0
0
-
0
-
0
-
0
-
R/W
R/W
R/W
R/W
Table 65:
Bit
31 to 4
HcBulkCurrentED register: bit description
Symbol
Description
BCED[27:0]
BulkCurrentED
: This is advanced to the next ED after the Host
Controller has served the present one. The Host Controller
continues processing the list from where it left off in the last
frame. When it reaches the end of the Bulk list, the Host
Controller checks the CLF (ControlListFilled) bit of HcControl. If
the CLF bit is not set, nothing is done. If the CLF bit is set, it
copies the content of HcBulkHeadED to HcBulkCurrentED and
clears the CLF bit. The HCD can only modify this register when
the BLE (BulkListEnable) bit of HcControl is cleared. When
HcControl is set, the HCD reads the instantaneous value of this
register. This is initially set to 0 to indicate the end of the Bulk list.
-
reserved
3 to 0
Table 66:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcDoneHead register: bit allocation
31
30
29
28
27
26
25
24
DH[27:20]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
DH[19:12]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
DH[11:4]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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