參數(shù)資料
型號(hào): ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 24/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
24 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Interrupt Pin register (address: 3DH):
This one-byte register is use to specify
which interrupt pin the device (or device function) uses. The bit description is given in
Table 22
.
A value of 1H corresponds to INTA#. A value of 2H corresponds to INTB#. A value of
3H corresponds to INTC#. A value of 4H corresponds to INTD#. Devices or functions
that do not use an interrupt pin must put a logic 0 in this register.
Minimum Grant and Maximum Latency registers (address: 3EH and 3FH):
The
Min_Gnt and Max_Lat registers are used to specify the desired settings of the device
for Latency Timer values. For both registers, the value specifies a period of time in
units of 250 ns. Values of 0 indicates that the device has no major requirements for
the settings of Latency Timers.The Min_Gnt register bit description is given in
Table 23
.
[1]
X is 1H for OHCI1 and OHCI2; X is 2H for EHCI.
The Max_Lat register bit description is given in
Table 24
.
[1]
XX is 2AH for OHCI1 and OHCI2; XX is 10H for EHCI.
8.2.2
Enhanced Host Controller-specific PCI registers
In addition to the PCI configuration header registers, EHCI needs some additional
PCI configuration space registers to indicate the serial bus release number,
downstream port wake-up event capability and adjust the USB bus frame length for
Start-of-Frame (SOF). The EHCI-specific PCI registers are given in
Table 25
.
SBRN register (address: 60H):
The SBRN register is a one-byte register, and the
bit description is given in
Table 26
. This register contains the release number of the
USB specification with which this USB Host Controller module is complaint.
Table 22:
Bit
7 to 0
Interrupt Pin register: bit description
Symbol
Access
IP[7:0]
R/W
Value
01H
Description
Interrupt Pin
: INTA# is the default interrupt pin used by the
ISP1561.
Table 23:
Bit
7 to 0
Min_Gnt register: bit description
Symbol
Access
Min_Gnt[7:0]
R/W
Value
0XH
[1]
Description
Min_Gnt
: It is used to specify how long a burst period the device
needs assuming a clock rate of 33 MHz.
Table 24:
Bit
7 to 0
Max_Lat register: but description
Symbol
Access
Max_Lat[7:0] R/W
Value
XXH
[1]
Description
Max_Lat
: It is used to specify how often the device needs to gain
access to the PCI bus.
Table 25:
Offset
60H
61H
62-63H
EHCI-specific PCI registers
Register
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Port Wake Capability (PORTWAKECAP)
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