參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 69/102頁
文件大小: 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
69 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.3 EHCI controller capability registers
Other than the OHCI Host Controller, there are some registers in EHCI that define the
capability of EHCI. The address range of these registers is located before the
operational registers.
11.3.1
CAPLENGTH/HCIVERSION register (address: value read from func2 of address
10H + 00H)
The bit allocation of this four-byte register is given in
Table 96
.
5
AUX_OUT_
FULL
AuxOutputFull
: IRQ12 is asserted whenever this bit is set to
logic 1, OUT_FULL (OutputFull) is set to logic 1, and the
IRQEn bit is set.
Inhibit Switch
: This bit reflects the state of the keyboard
inhibit switch. If set, the keyboard is active.
CmdData
: The Host Controller sets this bit to logic 0 on an I/O
write to port 60H and to logic 1 on an I/O write to port 64H.
Flag
: Nominally used as a system flag by software to indicate
a warm or cold boot.
InputFull
: Except for the case of a Gate A20 sequence, this
bit is set to logic 1 on an I/O write to address 60H or 64H.
While this bit is set to logic 1 and emulation is enabled, an
emulation interrupt condition exists.
OutputFull
: The Host Controller sets this bit to logic 0 on a
read of I/O port 60H. If IRQEn is set, AUX_OUT_FULL
(AuxOutputFull) determines which IRQ is activated. While this
bit is logic 0 and CharacterPending in HceControl is set to
logic 1, an emulation interrupt condition exists.
4
INH_SW
3
CMD_DATA
2
FLAG
1
IN_FULL
0
OUT_FULL
Table 95:
Bit
HceStatus register: bit description
…continued
Symbol
Description
Table 96:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
CAPLENGTH/HCIVERSION register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
23
22
21
20
19
18
17
16
HCIVERSION[15:8]
1
R
12
HCIVERSION[7:0]
0
R
4
CAPLENGTH[7:0]
0
R
1
R
15
0
R
14
0
R
13
0
R
11
1
R
10
0
R
9
1
R
8
0
R
7
0
R
6
0
R
5
0
R
3
0
R
2
0
R
1
0
R
0
0
R
0
R
0
R
1
R
1
R
0
R
0
R
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