參數(shù)資料
型號(hào): ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù): 82/102頁(yè)
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
82 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.4.9
PORTSC registers 1, 2, 3, 4 (address: value read from func2 of address 10H +
50H
+
(4 x Port Number
1)) where Port Number is 1, 2, 3,...N_Ports
The Port Status and Control (PORTSC) register (bit allocation:
Table 116
) is in the
auxiliary power well. It is only reset by hardware when the auxiliary power is initially
applied or in response to a Host Controller reset. The initial conditions of a port are:
No device connected
Port disabled
If the port has power control, software cannot change the state of the port until it sets
the port power bits. Software must not attempt to change the state of the port until the
power is stable on the port (max. delay is 20 ms from the transition).
Table 114: CONFIGFLAG register: bit allocation
Bit
31
Symbol
Reset
0
Access
-
Bit
23
Symbol
Reset
0
Access
-
Bit
15
Symbol
Reset
0
Access
-
Bit
7
Symbol
Reset
0
Access
-
30
29
28
27
26
25
24
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
22
21
20
19
18
17
16
reserved
0
-
0
-
0
-
0
-
0
-
0
-
9
0
-
8
14
13
12
11
10
reserved
0
-
6
0
-
5
0
-
4
0
-
3
0
-
2
0
-
1
0
-
0
reserved
0
-
CF
0
R/W
0
-
0
-
0
-
0
-
0
-
Table 115: CONFIGFLAG register: bit description
Bit
Symbol
31 to 1
-
0
CF
Description
reserved
Configure Flag
: The host software sets this bit as the last action in
its process of configuring the HC. This bit controls the default
port-routing control logic.
0 —
Port routing control logic default-routes each port to an
implementation dependent classic HC
1 —
Port routing control logic default-routes all ports to this HC
Table 116: PORTSC 1, 2, 3, 4 register: bit allocation
Bit
31
Symbol
Reset
0
Access
-
30
29
28
27
26
25
24
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
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