參數(shù)資料
型號(hào)： ISP1561BM
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線控制器
英文描述： ISP1561BM
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù)： 25/102頁(yè)
文件大?。?/td> 2875K
代理商： ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
25 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
FLADJ register (address: 61H):
This feature is used to adjust any offset from the
clock source that generates the clock that drives the SOF counter. When a new value
is written to these six bits, the length of the frame is adjusted. The bit allocation of the
register is given in
Table 27
.
PORTWAKECAP register (address: 62H):
The PORTWAKECAP register is a
two-byte register, and the bit description is given in
Table 29
. This register is used to
establish a policy about which ports are to be used for wake events. Bit positions
1 to 15 in the mask correspond to a physical port implemented on the current EHCI
controller. A logic 1 in a bit position indicates that a device connected below the port
can be enabled as a wake-up device and the port may be enabled for
disconnect/connect or overcurrent events as wake-up events. This is an information
only mask register. The bits in this register do not affect the actual operation of the
Table 26:
Bit
7 to 0
SBRN register: bit description
Symbol
Access
SBRN[7:0] R
Value
20H
Description
Serial Bus Specification Release Numbe
r: This register value is
to identify Serial Bus Specification Release 2.0. All other
combinations are reserved.
Table 27:
Bit
Symbol
Reset
Access
FLADJ register: bit allocation
7
reserved
0
-
6
5
4
3
2
1
0
FLADJ[5:0]
0
-
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 28:
Bit
7 to 6
5 to 0
FLADJ register: bit description
Symbol
Description
-
reserved
FLADJ[5:0]
Frame Length Timing Value
: Each decimal value change to this
register corresponds to 16 high-speed bit times. The SOF cycle time
(number of SOF counter clock periods to generate a SOF microframe
length) is equal to 59488
+
value in this field. The default value is
decimal 32 (20H), which gives a SOF cycle time of 60000.
FLADJ Value
SOF cycle time
(480 MHz)
59488
59504
59520
:
59984
60000
:
60480
60496
0 (00H)
1 (01H)
2 (02H)
:
31(1FH)
32 (20H)
:
62 (3EH)
63 (3FH)
相關(guān)PDF資料
PDF描述
ISP1562 Hi-Speed Universal Serial Bus PCI Host Controller
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
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ISP1561BM,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類(lèi)型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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