參數(shù)資料
型號(hào): ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù): 30/102頁(yè)
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
30 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
PMCSR_BSE register (address: value read from address 34H + 6H):
The
PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI
bridge specific functionality and is required for all PCI-to-PCI bridges. The bit
allocation of this register is given in
Table 37
.
[1]
Internally hardwired.
8
PMEE
PME Enabled
: Logic 1 enables the function to assert PME#. When
it is logic 0, PME# assertion is disabled. This bit defaults to logic 0 if
the function does not support the PME# generation from D3
cold
. If
the function supports PME# from D3
cold
, then this bit is sticky and
must be explicitly cleared by the operating system each time the
operating system is initially loaded. Functions that do not support
the PME# generation from any D-state (that is,
PMC[15:11] = 00000B), may hardwire this bit to be read-only
always returning logic 0 when read by system software.
reserved
Power State
: This two-bit field is used to determine the current
power state of the EHCI function and to set the function into a new
power state. The definition of the field values is given as:
7 to 2
1 to 0
-
PS[1:0]
00B —
for D0
01B —
for D1
10B —
for D2
11B —
for D3
hot
If the software attempts to write an unsupported, optional state to
this field, the write operation must complete normally on the bus;
however, the data is discarded and no status change occurs.
Table 36:
Bit
PMCSR register: bit description
…continued
Symbol
Description
Table 37:
Bit
Symbol
Reset
Access
PMCSR_BSE register: bit allocation
7
BPCC_En
B2_B3#
R
0
[1]
6
5
4
3
2
1
0
reserved
R
0
[1]
R
0
R
0
R
0
R
0
R
0
R
0
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