參數(shù)資料
型號: ISP1561BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: ISP1561BM
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數(shù): 46/102頁
文件大?。?/td> 2875K
代理商: ISP1561BM
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
46 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11.1.7
HcHCCA register (address: value read from func0 or func1 of address
10H
+
18H)
The HcHCCA register contains the physical address of the Host Controller
Communication Area (HCCA). The bit allocation is given in
Table 54
. The HCD
determines the alignment restrictions by writing all 1s to HcHCCA and reading the
content of HcHCCA. The alignment is evaluated by examining the number of zeroes
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
23
22
21
20
19
18
17
16
reserved
0
-
0
-
0
-
0
-
0
-
0
-
0
-
9
0
-
8
15
14
13
12
11
10
reserved
0
-
7
0
-
6
0
-
5
0
-
4
0
-
3
0
-
2
0
-
1
0
-
0
reserved
0
-
RHSC
0
R/W
FNO
0
R/W
UE
0
R/W
RD
0
R/W
SF
0
R/W
WDH
0
R/W
SO
0
R/W
Table 53:
Bit
31
HcInterruptDisable register: bit description
Symbol
Description
MIE
MasterInterruptEnable
: Logic 0 is ignored by the Host Controller.
Logic 1 disables interrupt generation due to events specified in
other bits of this register. This field is set after a hardware or
software reset. (Interrupts are disabled).
OC
0 —
ignore
30
1 —
disable interrupt generation due to Ownership Change
reserved
0 —
ignore
29 to 7
6
-
RHSC
1 —
disable interrupt generation due to Root Hub Status Change
0 —
ignore
5
FNO
1 —
disable interrupt generation due to Frame Number Overflow
0 —
ignore
4
UE
1 —
disable interrupt generation due to Unrecoverable Error
0 —
ignore
3
RD
1 —
disable interrupt generation due to Resume Detect
0 —
ignore
2
SF
1 —
disable interrupt generation due to Start-of-Frame
0 —
ignore
1
WDH
1 —
disable interrupt generation due to HcDoneHead Writeback
0 —
ignore
0
SO
1 —
disable interrupt generation due to Scheduling Overrun
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