Note (1): The status of these bits depends on the signal conditions. Default shown is for normal operation. The bits contribute to the RX Local" />
參數(shù)資料
型號(hào)： ISL35822IK
廠商： Intersil
文件頁數(shù)： 42/75頁
文件大小： 0K
描述： IC CLOCK/DATA RECOVERY 192EBGA-B
標(biāo)準(zhǔn)包裝： 90
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 1.575 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
47
Note (1): The status of these bits depends on the signal conditions. Default shown is for normal operation. The bits contribute to the RX Local Fault bit, see Table 77.
VENDOR-SPECIFIC PHY XS REGISTERS (4.C000’H TO 4.C00B’H)
Table 78. IEEE 10GBASE-X PHY XGXS STATUS REGISTER
MDIO REGISTER ADDRESSES = 4.24 (4.0018’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.24.15:13
Reserved
4.24.12
PHY XS
Lane_Align
1 = 4 Lanes Aligned
0 = Lanes not aligned
1’b(1)
RO
1 = Four 3G receive lanes (on egress path) are
aligned
4.24.11
Test_Pattern
Test Pattern Abilities
1’b
RO
1 = The device is able to generate test patterns for
10GBASE-X
4.24.10
PHYXSLpbk
Loopback Ability
1’b
RO
1 = Device is able to loopback
4.24.9:4
Reserved
4.24.3
Lane3 Sync
1 = Lane is Synchronized
0 = Lane not Synchronized
1’b(1)
RO
Reflects the PCS_SYNC byte alignment state
machine condition; not valid if not enabled in
device (see Table 80)
4.24.2
Lane2 Sync
1’b(1)
RO
4.24.1
Lane1 Sync
1’b(1)
RO
4.24.0
Lane0 Sync
1’b(1)
RO
Table 79. IEEE 10GBASE-X PHY XGXS TEST CONTROL REGISTER
MDIO REGISTER ADDRESS = 4.25 (4.0019’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.25.15:3
Reserved
4.25.2
PHY XS
TestPatEn
Receive Test Pattern
Enable
0’b
R/W
0 = Do not enable Receive test pattern
1 = Enable Receive test pattern
4.25.1:0
PHY XS TestPat
Type
Test pattern select (see
Table 72 for other test
patterns generated by
the ISL35822)
00’b
R/W
11 = Reserved
10 = Mixed frequency test pattern (Continuous /K/ = K28.5)
01 = Low frequency test pattern (repeat 0000011111 = K28.7)
00 = High frequency test pattern (repeat 0101010101 = D10.2)
Table 80. PHY XS CONTROL REGISTER 2
MDIO REGISTER ADDRESS = 4.49152 (4.C000’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49152.15:14
Test Mode
00’b
R/W
User should leave at 00’b
4.49152.13:12
Reserved
4.49152.11
PHY XS Clock
PSYNC
1’b
R/W
1 = Synchronize/align four lanes
0 = Do not synchronize/align four lanes
4.49152.10
PHY XS CODECENA 0 = disable
1 = enable
1’b
R/W
Internal 8B/10B Codec enable/disable
4.49152.9:8
PHY XS CDET[1:0]
Comma Detect
Select.
11’b
R/W
These bits individually enable positive and negative disparity
“comma” detection.
11 = Enable both positive and negative comma detection
10 = Enable positive comma detection only
01 = Enable negative comma detection only
00 = Disable comma detection
4.49152.7
PHY XS
DSKW_SM_EN
0 = disable(2)
1 = enable
0’b
R/W
Enable De-skew state machine control (3) . Forced enabled
by PHY XS XAUI_EN. May not operate correctly unless the
PHY XS PCS_SYNC_EN bit is also set.
4.49152.6:5
PHY XS RCLKMODE 11’b = Local
Reference
Clock(4)
11’b
R/W
Other values should only be used if incoming data is
frequency-synchronous with the local reference clock(4).
ISL35822
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