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參數(shù)資料
| 型號(hào)： | ISL35822IK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 27/75頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 192EBGA-B |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 無 |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.1875Gbps |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應(yīng)商設(shè)備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤 |
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Note (1): These 1-byte register values are merely copied by the ISL35822 from the I2C address space on Power-up or RESET, or on any DOM read operation. If the ‘Indirect
DOM Enable’ bit (Register bit 1.C018’h.2 Table 51) is not set, a four-lane external DOM device is expected to determine the values for these registers, according
Section 11.3 in the XENPAK MSA Rev 3.0 specification. A single one-lane DOM device system will provide the values from the single DOM device here. If the
‘Indirect DOM Enable’ bit is set, the values from the “Representative” (as defined by Register bits 1.C018’h.1:0 in Table 51), lane DOM are entered here.
Note (1): User writes to these bits are not valid unless the Command Status is Idle. The Command Status will not return to Idle until being read after command
completion (either Succeed or Failed).
Note (2): At the end of a hardware RESETN or a register 1.0.15 RESET operation, if the XP_ENA pin is asserted, and the DOM control bits are set in 1.32890 (1.807A),
the ISL35822 will automatically begin a ‘Periodic update, fastest rate read’ operation.
Note (3): The rates of the periodic reads are determined by bits 4:3 of register 1.49176 (1.C018’h), see Table 51.
VENDOR-SPECIFIC PMA/PMD AND GPIO REGISTERS (1.C001’H TO 1.C01D’H)
Note (1): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): Internal test purposes only.
Note (3): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown firs
t.
Note (4): Optimum value to meet output templates. Contact BitBlitz for recommended value.
1.41076.3
LBC_High
1 = Warning Set
0 = Warning Not Set
0’b
RO
Laser Bias Current High Warning
1.41076.2
LBC_Low
0’b
RO
Laser Bias Current Low Warning
1.41076.1
LOP_High
0’b
RO
Laser Output Power High Warning
1.41076.0
LOP_Low
0’b
RO
Laser Output Power Low Warning
1.41077.15:8
Reserved
00’h
1.41077.7
ROP_High
1 = Warning Set
0 = Warn. Not Set
0’b
RO
Receive Optical Power High Warning
1.41077.6
ROP_Low
0’b
RO
Receive Optical Power Low Warning
1.41077.5:0
Reserved
00’h
Table 37. XENPAK DOM WARNING FLAGS REGISTER (Continued)
MDIO REGISTER, ADDRESS = 1.41076:7 (1.A074:5’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
Table 38. XENPAK DOM OPERATION CONTROL AND STATUS REGISTER
MDIO REGISTER, ADDRESS = 1.41216 (1.A100’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.41216.15:4
Reserved
0000’h
1.41216.3:2
DOM
Command
Status(1)
Current Status of DOM
Command
00’b
RO
11 = Command failed
10 = Command in progress/Queued
01 = Command complete w success
00 = Idle
1.41216.1:0
DOM
Command
Type(1)
NVR operation to be
performed
11’b(2)
R/W
00 = Single DOM Read operation
01 = Periodic update, slowest rate(3)
10 = Periodic update, intermediate rate(3)
11 = Periodic update, fastest rate(3)
Table 39. PMA CONTROL 2 REGISTER
MDIO REGISTER, ADDRESS = 1.49153 (1.C001’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49153.15
PMA DC_O_DIS
1 = Disable, 0 = normal
0’b(1)
R/W
PMA DC Offset Disable
1.49153.14
Test
0 = normal
0’b(2) (1)
R/W
User must keep at 0.
1.49153.13
Amplitude adjust
1,0’h(1) (3)
R/W
Optimizing Setting, TBD(4)
1.49153.12:11
Reserved
0’h
1.49153.10:8
PMA_LOS_TH
0’h = 160mVp-p
1’h = 240mVp-p
2’h = 200mVp-p
3’h = 120mVp-p
4’h = 80mVp-p
else = 160mVp-p
LX4: (3) 0’h,
CX4:
03’h(1)
R/W
Set the threshold voltage for the Loss Of
Signal (LOS) detection circuit in
PMA/PMD. Nominal levels are listed for
each control value. Note that the
differential peak-to-peak value is twice that
listed.
1.49153.7:0
Reserved
00’h
ISL35822
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