參數(shù)資料
型號: ISL35822IK
廠商: Intersil
文件頁數(shù): 1/75頁
文件大?。?/td> 0K
描述: IC CLOCK/DATA RECOVERY 192EBGA-B
標(biāo)準(zhǔn)包裝: 90
類型: 時鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
輸入: CML
輸出: CML,CMOS
電路數(shù): 1
比率 - 輸入:輸出: 8:8
差分 - 輸入:輸出: 是/是
頻率 - 最大: 3.1875Gbps
電源電壓: 1.425 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 192-EBGA
供應(yīng)商設(shè)備封裝: 192-EBGA-B(17x17)
包裝: 托盤
1
FN6165.0.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL35822
Octal 2.488Gbps to 3.187Gbps/
Lane Retimer
Features
8 Lanes of Clock & Data Recovery and Retiming; 4 in
Each Direction
Differential Input/Output
Wide Operating Data Rate Range: 2.488Gbps to
3.1875Gbps, and 1.244Gbps to 1.59325Gbps
Ultra Low-Power Operation (163mW typical per lane,
1300mW typical total consumption, LX4 mode)
Low Power Version Available for LX4 Applications
17mm Square Low Profile 192 pin 1.0mm Pitch EBGA-B
Package
Compliant to the IEEE 802.3 10GBASE-LX4(WWDM),
10GBASE-CX4, and XAUI Specifications
Reset Jitter Domain
Meets 802.3ae and 802.3ak Jitter Requirements with
Significant Margin
Received Data Aligned to Local Reference Clock for
Retransmission
Increase Driving Distance
LX4: Up to 40 inches of FR-4 Traces or 500 Meters of
MMF Fiber at 3.1875Gbps
CX4: Over 15 meters of Compatible Cable
Deskewing and Lane-to-Lane Alignment
0.13mm Pure-Digital CMOS Technology
1.5V Core Supply, Control I/O 2.5V Tolerant
Clock Compensation
Tx/Rx Rate Matching via IDLE Insertion/Deletion up to
±100ppm Clock Difference
Receive Signal Detect and 16 Levels of Receiver
Equalization for Media Compensation
CML CX4 Transmission Output with 16 Settable Levels of
Pre-Emphasis, Eight on XAUI Side
Single-Ended or Differential Input Lower-Speed Reference
Clock
Ease of Testing
Complete Suite of Ingress-Egress Loopbacks
Full 802.3ae Pattern Generation and Test, including
CJPAT & CRPAT
PRBS (both 223-1 and 13458 byte) Built-In Self Tests,
Error Flags and Count Output
JTAG and AC-JTAG Boundary Scan
Long Run Length (512 bit) Frequency Lock Ideal for
Proprietary Encoding Schemes
Extensive Configuration and Status Reporting via 802.3
Clause 45 Compliant MDC/MDIO Serial Interface
Automatic Load of ISL35822 Control and all XENPAK
Registers from EEPROM or DOM Circuit
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Egress 2
Egress 0
Ingress 2
Ingress 0
Clock Multiplier
RFCP
RFCN
RX0N
RX0P
3.125G
Receive
Parallel
Data
MDIO/MDC
Register File
TX0N
TX0P
Deserializer
and Comma
Detector
8B/10B
Decoder
8B/10B
Encoder
& Mux
Clock &
Data
Recovery
Receive
FIFO
I2C Interface
MDC
MDIO
SDA
SCL
Ingress 3
Egress 3
Ingress 1
Egress 1
Data Sheet
June 29, 2005
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