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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 83/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
10.7.1 AsicCtrl
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x01
Access Mode ................ Read Only
Width ............................ 16 bits
AsicCtrl supplies the value for the least significant byte of the AsicCtrl register and the WakeEvent register.
BIT
BIT NAME
0
Reserved
Reserved for future use.
1
ExpRomSize
Expansion ROM Size. ExpRomSize corresponds to the ExpRomSize bit in the
AsicCtrl register.
2
TxLargeEnable
Transmit Large Frames Enable. TxLargeEnable corresponds to the
TxLargeEnable bit in the AsicCtrl register.
3
RxLargeEnable
Receive Large Frames Enable. RxLargeEnable corresponds to the
RxLargeEnable bit in the AsicCtrl register.
4
ExpRomDisable
Expansion
ROM
ExpRomDisable bit in the AsicCtrl register.
5
PhySpeed10
Physical Layer Device Speed 10Mbps. PhySpeed10 corresponds to the
PhySpeed10 bit in the AsicCtrl register.
6
PhySpeed100
Physical Layer Device Speed 100Mbps. PhySpeed100 corresponds to the
PhySpeed100 bit in the AsicCtrl register.
7
PhyMedia
Physical Layer Device Media. PhyMedia corresponds to the PhyMedia bit in
the AsicCtrl register.
11..8
Reserved
Reserved for future use.
12
Vaux
Vaux. Vaux corresponds to the Vaux bit in the PowerMgmtCap register.
13
MultiFunction
Multi-Function
Device.
Reserved/MultiFunction bit in the AsicCtrl register.
14
Reserved
Reserved for future use.
15
WakeOnLanEnable
Wake
On
LAN
Enable.
WakeOnLanEnable bit in the WakeEvent register.
10.7.2 ConfigParm
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x00
Access Mode ................ Read Only
Width ............................ 16 bits
BIT
BIT NAME
0
FastBackToBack
Fast Back to Back. FastBackToBack corresponds to the FastBackToBack bit
in the ConfigStatus register.
1
Lower1Meg
Lower 1 Megabyte. Lower1Meg corresponds to bit 1 of the MemMapType bit
in the MemBaseAddress register.
IP100-DS-R03
May 27, 2003
83/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
Disable.
ExpRomDisable
corresponds
to
the
MultiFunction
corresponds
to
the
WakeOnLanEnable
corresponds
to
the
BIT DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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