參數(shù)資料
型號: IP100
英文描述: PCI 10/100M Single Chip Ethernet Controller
中文描述: 單芯片的PCI個10/100M以太網(wǎng)控制器
文件頁數(shù): 35/92頁
文件大小: 2801K
代理商: IP100
IP100
10.4 LAN I/O Registers
IP100-DS-R03
May 27, 2003
35/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
The host interacts with the IP100 mainly through slave registers, which occupy 128 bytes in the host system’s I/O
space, memory space, or both. Generally, registers are referred to as “I/O registers”, implying that the registers
may in fact be mapped and accessed by the host system in memory space. I/O registers must be accessed with
instructions that are no larger than the bit-width of that register.
The IP100 LAN I/0 register layout is show in Figure 13.
BYTE 3
BYTE 2
BYTE 1
HashTable[63..32]
HashTable[31..0]
PhyCtrl
TxReleaseThresh
MaxFrameSize
StationAddress[31..0]
MACCtrl1
IntStatus
IntStatusAck
TxStatus
WakeEvent
ExpRomAddr
FIFOCtrl
EepromCtrl
AsicCtrl
ForceEvent
FunctionEventMask
FunctionEvent
FunctionPresentState
RxDMAPollPeriod
Thresh
RxDMAStatus
TxDMAPollPeriod
Thresh
TxDMAListPtr
DMACtrl
BYTE 0
ADDR OFFSET
0x64
0x60
0x5C
0x58
0x54
0x50
0x4C
0x48
0x44
0x40
0x38
0x34
0x30
0x2C
0x28
0x24
0x20
0x1C
0x18
0x14
ReceiveMode
StationAddress[47..32]
MACCtrl0
IntEnable
ExpRomData
EepromData
DebugCtrl
Countdown
RxDMAUrgent-
RxDMABurst-
Thresh
TxDMABurst-
Thresh
0x0C
0x08
TxDMAUrgent-
0x04
0x00
FIGURE 13 : IP100 I/O Register Map
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