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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 23/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.1.5 Auto-Negotiation Advertisement
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x04
Default .......................... 0x01E1
Width ............................ 16 bits
BIT
BIT NAME
15
Next Page capable
IP100-DS-R03
May 27, 2003
23/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
R/W
R/W
BIT DESCRIPTION
1 = Next Page capable.
0 = Next Page incapable.
Reserved for future use.
1 = Remote Fault supported.
0 = Remote Fault not supported.
Reserved for future use.
1 = Pause function supported.
0 = Pause not supported.
1 = 100BASE-T4 capable.
0 = 100BASE-T4 incapable.
1 = PHY 100BASE-TX Full Duplex capable.
0 = PHY not 100BASE-TX Full Duplex capable.
1 = PHY 100BASE-TX Half Duplex capable.
0 = PHY not 100BASE-TX Half Duplex capable.
1 = PHY 10BASE-T Full Duplex capable.
0 = PHY not 10BASE-T Full Duplex capable.
1 = PHY 10BASE-T Half Duplex capable.
0 = PHY not 10BASE-T Half Duplex capable.
IEEE 802.3 selector field
14
13
Reserved
Remote Fault
N/A
R/W
12..11
10
Reserved
Pause
N/A
R/W
9
100BASE-T4
R/W
8
100BASE-TX Full
Duplex
100BASE-TX Half
Duplex
10BASE-T Full
Duplex
10BASE-T Half
Duplex
Selector Field
R/W
7
R/W
6
R/W
5
R/W
4..0
R/W
10.1.6 Auto-Negotiation Link Partner Ability
Class............................. PHY Registers
Access Method............. Accessed through PhyCtrl register
Register Address.......... 0x05
Default .......................... 0x0000
Width ............................ 16 bits
BIT
BIT NAME
15
Next Page
R/W
R
BIT DESCRIPTION
1 = Next Page capable.
0 = Next Page incapable.
1 = Link Code Word received.
0 = Link Code Word not received.
1 = Remote Fault detected.
0 = Remote Fault not detected.
If Remote Fault is a logic 1, then the Remote Fault bit of the
Status Register register will be a logic 1.
Reserved for future use.
14
Acknowledge
R
13
Remote Fault
R
12..10
Reserved
N/A
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PDF描述 |
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| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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