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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
46/92
IP100-DS-R03
May 27, 2003
BIT
31..16
BIT NAME
Reserved
R/W
N/A
BIT DESCRIPTION
Reserved for future use.
10.4.11 FunctionEvent
Class............................. LAN I/O Registers, CardBus Status Change
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x24
Default Value ................ 0x00000000
Width ............................ 32 bits
FunctionEvent contains the bits which can be used to generate status change interrupts, depending upon the
setting of the FunctionEventMask register. This register is disabled when the CardBus bit of AsicCtrl is low.
BIT
BIT NAME
R/W
3..0
Reserved
N/A
Reserved for future use.
4
GWAKE
R/W
GWAKE. GWAKE is a logic 1 and remains a logic 1 when the
GWAKE bit of the FunctionPresentState register is a logic 1.
GWAKE is cleared by writing a logic 1 to GWAKE. Writing a logic 1
to GWAKE also clears the PmeStatus bit of the PowerMgmtCtrl
register.
14..5
Reserved
N/A
Reserved for future use.
15
INTR
R/W
INTR. INTR is a logic 1 whenever an interrupt is pending regardless
of the INTR bit in the FunctionEventMask register. INTR is cleared
by writing a logic 1 to INTR.
31..16
Reserved
N/A
Reserved for future use.
10.4.12 FunctionEventMask
Class............................. LAN I/O Registers, CardBus Status Change
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x28
Default Value ................ 0x00000000
Width ............................ 32 bits
FunctionEventMask masks the FunctionEvent register. This register is disabled when the CardBus bit of AsicCtrl
is low.
BIT
BIT NAME
R/W
3..0
Reserved
N/A
Reserved for future use.
4
GWAKE
R/W
GWAKE. If GWAKE is a logic 1, and WKUP is a logic 1 the GWAKE
bit of the FunctionEvent register may assert the CSTSCHGN signal.
13..5
Reserved
N/A
Reserved for future use.
14
WKUP
R/W
WKUP. If WKUP is a logic 1, all events (WriteProtect, Ready/Busy,
BatterryVoltageDetect, and GWAKE) may assert the CSTSCHGN
signal.
15
INTR
R/W
INTR. If INTR is a logic 1, setting the INTR bit of the FunctionEvent
register will assert the INTAN.
31..16
Reserved
N/A
Reserved for future use.
BIT DESCRIPTION
BIT DESCRIPTION