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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 67/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.5.11 MulticastFramesReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7f
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
7..0
MulticastFrames-
ReceivedOk
IP100-DS-R03
May 27, 2003
67/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
R/W
R/W
BIT DESCRIPTION
Multicast Frames Received OK is the count of the number of frames
that are successfully received to a group destination address other
than
the
broadcast
address
MulticastFramesReceivedOk does not include frames received with
frames too long, FCS, length or alignment errors, or frames lost due
to
internal
MAC
sublayer
MulticastFramesReceivedOk will wrap around to zero after reaching
0xFF. See IEEE 802.3 Clause 30.3.1.1.21.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when MulticastFramesReceivedOk reaches a
value of 0xC0. MulticastFramesReceivedOk is enabled by writing a
logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of MulticastFramesReceivedOk also clears the register.
(0xFFFFFFFFFFFF).
error
(i.e.
overrun).
10.5.12 MulticastFramesTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7e
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
7..0
Multicast-
FramesTransmitted-
Ok
R/W
R/W
BIT DESCRIPTION
Multicast Frames Transmitted OK is a count of the number of frames
that are successfully transmitted to a group destination address
other
than
the
broadcast
MulticastFramesTransmittedOk will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.18.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when MulticastFramesTransmittedOk reaches a
value of 0xC0. MulticastFramesTransmittedOk is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of MulticastFramesTransmittedOk also clears the register.
address
(0xFFFFFFFFFFFF).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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