參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 48/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
10.4.15 IntEnable
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x4c
Default .......................... 0x0000
Width ............................ 16 bits
Enables individual interrupts as specified in the IntStatus register. Setting a bit in IntEnable will allow the specific
source to generate an interrupt on the PCI bus. IntEnable is cleared by a read of IntStatusAck.
BIT
BIT NAME
R/W
0
Reserved
N/A
Reserved for future use.
1
EnHostError
R/W
Enable Host Error Interrupt. Enables the HostError interrupt.
2
EnTxComplete
R/W
Enable Transmit Complete Interrupt. Enables the TxComplete
interrupt.
3
EnMACControlFrame
R/W
Enable MAC Control Frame Interrupt. Enables the MACControlFrame
interrupt.
4
EnRxComplete
R/W
Enable Receive Complete Interrupt. Enables the RxComplete interrupt.
5
Reserved
R/W
Reserved for future use.
6
EnIntRequested
R/W
Enable Interrupt Requested Interrupt. Enables the IntRequested
interrupt.
7
EnUpdateStats
R/W
Enable Update Stats Interrupt. Enables the UpdateStats interrupt.
8
EnLinkEvent
R/W
Enable Link Event Interrupt. Enables the LinkEvent interrupt.
9
EnTxDMAComplete
R/W
Enable Transmit DMA Complete Interrupt. Enables the TxDMAComplete
interrupt.
10
EnRxDMAComplete
R/W
Enable Receive DMA Complete Interrupt. Enables the RxD-MAComplete
interrupt.
11
Reserved/
EnModemInt
R/W
Enable Modem Interrupt. Enables the Reserved/ModemInt interrupt.
15..12
Reserved
N/A
Reserved for future use.
10.4.16 IntStatus
Class….......................... LAN I/O Registers, Interrupt
Base Address …............ IoBaseAddress register value
Address Offset …........... 0x4e
Default …....................... 0x0000
Width …......................... 16 bits
IntStatus indicates the source of interrupts and indications on the IP100. All bits except InterruptStatus are the
interrupt causing sources for the IP100. Each interrupt source can be individually disabled using the IntEnable
register. The host system may acknowledge most interrupts by writing a logic 1 into the corresponding IntStatus
bit, which will cause the IP100 to clear the interrupt indication.
BIT
BIT NAME
R/W
0
InterruptStatus
R/W
Interrupt Status. InterruptStatus is a logic 1 when the IP100 is driving
the bus interrupt signal (INTAN). InterruptStatus is a logical OR of all
the interrupt causing sources after they have been filtered through the
IntEnable register.
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
48/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
N/A,
Reserved for future use.
BIT DESCRIPTION
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