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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 61/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
10.4.35 WakeEvent
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x45
Default .......................... 0x00
Width ............................ 8 bits
WakeEvent contains enable bits to control which types of events can generate a wake event to the host system.
WakeEvent also contains status bits indicating the specific wake events which have occurred.
BIT
BIT NAME
R/W
0
WakePktEnable
R/W
Wake Packet Enable. If WakePktEnable is a logic 1, the IP100 may
generate wake events via a PCI interrupt due to Wake Packet
reception. The PmeEn bit in the PowerMgmtCtrl register must be set
in order for WakePktEnable to be recognized. WakePktEnable has
no effect in power mode D0.
1
MagicPktEnable
R/W
Magic Packet Enable. If MagicPktEnable is a logic 1, the IP100 may
generate wake events via a PCI interrupt due to Magic Packet
reception. The PmeEn bit in the PowerMgmtCtrl register must be set
in order for MagicPktEnable to be recognized. MagicPktEnable has
no effect in power mode D0.
2
LinkEventEnable
R/W
Link Event Enable. If LinkEventEnable is a logic 1, the IP100 may
generate wake events via a PCI interrupt due to a change in link
status (cable connect or disconnect). The PmeEn bit in the
PowerMgmtCtrl register must be set in order for LinkEventEnable to
be recognized. LinkEventEnable has no effect in power mode D0.
3
WakePolarity
R/W
Wake Polarity. If WakePolarity is a logic 1, the WAKE signal will be
asserted HIGH. If WakePolarity is a logic 0, the WAKE signal will be
asserted LOW.
4
WakePktEvent
R
Wake Packet Event. If WakePktEvent is a logic 1, a wake packet
(which meets the reception criteria set by the host system) has been
received. WakePktEnable must be a logic 1 for WakePktEvent to
operate. WakePktEvent is cleared following a read of the
WakeEvent register.
5
MagicPktEvent
R
Magic Packet Event. If MagicPktEvent is a logic 1, a Magic Packet
packet has been received. MagicPktEnable must be a logic 1 for
MagicPktEvent to operate. MagicPktEvent is cleared following a
read of the WakeEvent register.
6
LinkEvent
R
Link Event. If LinkEvent is a logic 1, a link status event has occurred.
LinkEventEnable must be a logic 1 for LinkEvent to operate.
LinkEvent is cleared following a read of the WakeEvent register.
7
WakeOnLanEnable
R/W
Wake On LAN Enable. If WakeOnLanEnable is a logic 1, the IP100
is in WakeOnLan mode regardless of the power management
register settings in the configuration space. WakeOnLanEnable is
loaded from the WakeOnLanEnable bit of AsicCtrl field within the
EEPROM.
IP100-DS-R03
May 27, 2003
61/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
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