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| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 14/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
14/92
IP100-DS-R03
May 27, 2003
HOST SYSTEM MEMORY
RFD 1
RFD 2
RFD n
FIGURE 7: RxDMA List Shown in Ring
The host system must create a RxDMAList and the
associated buffers prior to reception of a frame. One
approach calls for the host system to allocate a
block of full size (i.e. large enough to hold a
maximum size Ethernet frame of 1518 bytes) frame
buffers in system data space and create RFDs that
point to them. Another approach is for the host
system to request the buffers from the protocol
ahead of time.
After reset, the IP100 receive function is disabled.
Once the RxEnable bit is set, frames will be
received
according
to
programmed in ReceiveMode register. Reception
can be disabled by setting the RxDisable bit. If set
while a frame is being received, RxDisable only
takes effect after the active frame reception is
finished.The receive function begins with the
RxDMA Logic in the idle state. The RxDMA Logic
will begin processing a RxDMAList as soon as a
non-zero address is written into the RxDMAListPtr
register. The host system creates a RFD with the
addresses and lengths of the buffers to be used and
programs the RxDMAListPtr register to point to the
head of the list. The host system must program a
zero into the RxDMANextPtr of the last RFD to
indicate the end of the RxDMAList. When a frame is
received in the RxFIFO, the IP100 fetches the
fragment address and fragment length values one
by one from the current RFD, and writes these
values into internal registers which control data
transfer operations. Similar to TxDMA, the RxDMA
Logic will return to the idle state when the
the
matching
mode
RxDMAListPtr register is zero.
For RxDMA lists configured as a ring, the host
system should clear the RxDMAComplete bit within
the ReceiveFrameStatus field of the RFD from
which the host system has finished reading data. If
RxDMAPollPeriod is zero the host system should
also issue a RxDMAResume in case the IP100 has
halted due to detection of a set RxDMAComplete bit
within the ReceiveFrameStatus field of the next
RFD in the ring. If the IP100 fetches a
RxDMAListPtr for a RFD that has already been
used (a RFD in which the RxDMAComplete bit is set
in ReceiveFrameStatus), the RxDMA Logic will
either assert an implicit RxDMAHalt or, if the
RxDMAPollPeriod register is set to a non-zero value,
the RxDMA Logic will automatically recheck
RxDMAComplete periodically until it is cleared.
The IP100 can be configured to generate a
RxDMAComplete interrupt when RxDMA completes
a frame transfer. In response to a RxDMAComplete
interrupt, the host system must examine the
ReceiveFrameStatus field in the RFD of the
received frame to determine the size of the frame
and whether there were any errors. The host system
must then copy the frame out of the receive buffers,
if needed.
In general, when the host system enters its interrupt
service routine, multiple frames may have been
transferred by RxDMA. The host system can read
RxDMAListPtr to determine which RFDs in the list
have been used. The host system begins at the
head of the RFD list, and traverses the list until it
reaches the RFD whose address matches
RxDMAListPtr. However, since I/O operations are
costly,
it
is
more
efficient
RxDMAComplete bit in each RFD to determine
which frames have been transferred by RxDMA.
In some host systems, it may be desirable to copy
received frame data out of the scatter buffer to the
protocol buffer while the frame is still being
transferred by RxDMA. The RxDMAStatus register
is provided for this purpose. If the host system sets
the RxDMAHalt bit in the DMACtrl register, reads
the RxDMAListPtr register and the RxDMAStatus
register, then sets the RxDMAResume bit in the
DMACtrl register, the host system can determine
how much of the frame has been transferred by
RxDMA. The RxDMAStatus register indicates the
to
use
the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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