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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 57/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
10.4.27 RxDMAUrgentThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x15
Default .......................... 0x04
Width ............................ 8 bits
RxDMAUrgentThresh sets a threshold at which the receive DMA logic will make a urgent bus master request. A
urgent receive DMA request will have priority over all other requests on the IP100. The urgent bus request is
made when the free space in the receive FIFO falls below the value in RxDMAUrgentThresh. A receive DMA
urgent request is not subject to the RxDMABurstThresh constraint. When the receive FIFO is close to overrun,
burst efficiency is sacrificed in favor of requesting the bus as quickly as possible. The value in
RxDMAUrgentThresh represents free space in the receive FIFO in terms of 32-byte portions.
BIT
BIT NAME
R/W
4..0
RxDMAUrgentThresh
R/W
Receive DMA Urgent Threshold. RxDMAUrgentThresh is the
minimum number of 32-byte words which must be available in the
receive FIFO to avoid a receive DMA urgent request.
7..5
Reserved
N/A
Reserved for future use.
10.4.28 StationAddress
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x54, 0x56, 0x58
Default .......................... 0x000000000000
Width ............................ 48 bits (accessible as 3, 16 bit words)
StationAddress is used to define the individual destination address that the IP100 will respond to when receiving
frames. Network addresses are generally specified in the form of 01:23:45:67:89:ab, where the bytes are received
left to right, and the bits within each byte are received right to left (Isb to msb). The actual transmitted and received
bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101.
BIT
BIT NAME
R/W
15..0
StationAddressWord0
R/W
The least significant word of the station address, corresponding to
address 0x54.
31..16 StationAddressWord1
R/W
The second least significant word of the station address, corresponding
to address 0x56.
47..32 StationAddressWord2
R/W
The most significant word of the station address, corresponding to
address 0x58.
The address comparison logic will compare the first 16 received destination address bits against
StationAddressWord0, the second 16 received destination address bits against StationAddressWord1, and the
third 16 received destination address bits against StationAddressWord2. The value set in StationAddress is not
inserted into the source address field of frames transmitted by the IP100. The source address field for every
frame must be specified by the host system as part of the frame data contents.
10.4.29 TxDMABurstThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x08
Default .......................... 0x08
Width ............................ 8 bits
IP100-DS-R03
May 27, 2003
57/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
BIT DESCRIPTION
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相關代理商/技術參數(shù) |
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|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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