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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 20/92頁 |
| 文件大小： | 2801K |
| 代理商： | IP100 |
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IP100
10 Registers and Data Structures
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
20/92
IP100-DS-R03
May 27, 2003
10.1 PHY Registers
The IP100 includes a full set of PHY registers which can be accessed through the internal MDC/MDIO interface.
The MAC and PHY, although integrated, act as if they are separate. The PHY registers must be accessed
throught the PhyCtrl register.
10.1.1 Control Register
Class............................. PHY Registers, Control
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x00
Default .......................... 0x3100
Width ............................ 16 bits
BIT
BIT NAME
R/W
15
Reset
R/W
1 = Software Reset (self clearing). While the IP100 is resetting,
Reset will remain a logic 1 and write attempts to any PHY Registers
are not accepted.
0 = Normal operation.
14
Loopback
R/W
1 = PHY loopback mode. When Loopback is a logic 1, the IP100 will
be isolated from the network media. All transmit data from the MAC
will return to the MAC as receive data. Collision indications are
disabled unless Collision Test is a logic 1.
0 = Normal operation.
13
Speed
R/W
1 = 100 Mb/s.
0 = 10 Mb/s.
12
Auto-Negotiation
R/W
1 = Auto-negotiation enabled.
0 = Auto-negotiation disabled.
11
Power Down
R/W
1 = PHY power down. When Power Down is a logic 1, the IP100
PHY will enter Power Down mode. While in Power Down mode, the
IP100 PHY will not respond to transmit data, or received data but will
respond to management transactions.
0 = Normal operation.
10
Isolate
R/W
1 = Isolate PHY. When Isolate is a logic 1, the IP100 PHY will be
isolated from the MAC. When isolated, the IP100 will not respond to
transmit or receive data, but will respond to management
transactions.
0 = Normal operation.
9
Restart
Auto-Negotiation
Auto-Negotiation is a logic 1, the IP100 will restart Auto-Negotiation,
depending on the Auto-Negotiation bit. If the Auto-Negotiation bit is
a logic 0, then Restart Auto-Negotiation has no effect.
0 = Normal operation.
8
Duplex Mode
R/W
1 = Full duplex.
0 = Half duplex.
BIT DESCRIPTION
R/W
1 = Restart auto-negotiation (self clearing). When Restart
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
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| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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