參數(shù)資料
型號(hào): iMC010FLSA
廠商: Intel Corp.
英文描述: 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲(chǔ)器卡)
中文描述: 5伏2系列閃存卡(5V的系列2閃速存儲(chǔ)器卡)
文件頁(yè)數(shù): 7/51頁(yè)
文件大?。?/td> 827K
代理商: IMC010FLSA
E
2.0
iMC002/004/010/020FLSA
7
PRELIMINARY
SERIES 2 ARCHITECTURE
OVERVIEW
The Series 2 Flash Memory Card contains a 2 to 20
MB flash memory array consisting of 2 to 20
28F008SA FlashFile memory devices.
28F008SA contains sixteen individually-erasable,
64 Kbyte blocks; therefore, the flash memory card
contains from 32 to 320 device blocks. It also
contains two Card Control Logic devices that
manage the external interface, address decoding,
and component management logic. (Refer to Figure
1 for a block diagram.)
Each
To support PCMCIA-compatible word-wide access,
devices are paired so that each accessible memory
block is 64 KWords (see Figure 2). Card logic
allows the system to write or read one word at a
time, or one byte at a time by referencing the high
or low byte. Erasure can be performed on the entire
block
pair
(high
and
simultaneously), or on the high or low byte portion
separately.
low
device
blocks
Also in accordance with PCMCIA specifications this
product supports byte-wide operation, in which the
flash array is divided into 128K x 8 bit device
blocks. In this configuration, odd bytes are
multiplexed onto the low byte data bus.
Series 2 Flash Memory Cards offer additional
features over the bulk erase flash card product
family (refer to iMC001FLKA, iMC002FLKA and
iMC004FLKA datasheets). Some of the more
notable enhancements
capability, erase blocking, internal write/erase
automation, erase suspension to read, Component
Management Registers (CMRs) that provide
software control of device-level functions and a
deep-sleep mode.
include:
high
density
Erase blocking facilitates solid-state storage
applications
by
allowing
reclamation. Multiple 64-Kbyte blocks may be
simultaneously erased within the memory card as
long as not more than one block per device is
erasing. This shortens the total time required for
erasure, but requires additional supply current. A
block typically requires 1.6 seconds to erase. Each
memory block can be erased and completely
written 100,000 times.
selective
memory
Erase suspend allows the system to temporarily
interrupt a block erase operation. This mode
permits reads from alternate device blocks while
that same device contains an erasing block. Upon
completion of the read operation, erasure of the
suspended block must be resumed.
Write/erase automation simplifies the system
software interface to the card. A two-step command
sequence initiates write or erase operations and
provides additional data security. Internal device
circuits automatically execute the algorithms and
timings necessary for data-write or block-erase
operations, including verifications for long-term data
integrity. While performing either data-write or
block-erase, the memory card interface reflects this
by bringing its RDY/BSY# (Ready/Busy) pin low.
This output goes high when the operation
completes. This feature reduces CPU overhead and
allows software polling or hardware interrupt
mechanisms. Writing memory data is achieved in
single byte or word increments, typically in 6 μs.
Read access time is 150 ns or less over the entire
operating temperature range.
The reset power-down mode reduces power
consumption to less than 60 μA to help extend
battery life of portable host systems. Activated
through software control, this mode optionally
affects the entire flash array (global reset power-
down register) or specific device pairs (sleep control
register).
3.0
PCMCIA/JEIDA INTERFACE
The Series 2 Flash Memory Card interface supports
the PCMCIA 2.1 and JEIDA 4.1 68-pin card format
(see Tables 1 and 2). Detailed specifications are
described in the
PC Card Standard
, Release 2.1,
July, 1993, published by PCMCIA. The Series 2
Card conforms to the requirements of both Release
1 and Release 2 of the
PC Card Standard
.
Series 2 Card pin definitions are equivalent to the
bulk erase flash card except that certain No
Connects are now used. A
22
through A
24
, RST
(Reset), and RDY/BSY# (Ready/Busy) have pin
assignments as set by the PCMCIA standard.
NOTE:
The READY/BUSY signal is abbreviated as
RDY/BSY# by PCMCIA (card level) and as
RY/BY# by JEDEC (component level).
The outer shell of the Series 2 card meets all
PCMCIA/JEIDA Type 1 mechanical specifications.
See Figure 19 for mechanical dimensions.
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