參數(shù)資料
型號: iMC010FLSA
廠商: Intel Corp.
英文描述: 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲器卡)
中文描述: 5伏2系列閃存卡(5V的系列2閃速存儲器卡)
文件頁數(shù): 16/51頁
文件大小: 827K
代理商: IMC010FLSA
iMC002/004/010/020FLSA
E
16
PRELIMINARY
GLOBAL RESET POWER-DOWN REGISTER
(CONFIGURATION AND STATUS REGISTER)
(Read/Write Register)
1 = POWER-DOWN
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ZEROES
4002H
RP
ZEROES
FIG6
Figure 6. Global Reset Power-Down Register (PCMCIA)
The RP Bit Enables Reset Power-Down of All Flash Memory Devices
13.3
Card Status Register (Intel)
The read-only, card status register (Attribute
Memory Plane Address 4100H, Figure 7) returns
generalized status of the Series 2 Card and its
CMRs.
Bit 0 (RDY/BSY#) reflects the card’s RDY/BSY#
(Ready-Busy) output. Software polling of this bit
provides data-write or block-erase operation status.
A zero indicates a busy device(s) in the card.
Bit 1 (WP) reports the position of the card’s Write
Protection switch with 1 indicating write protected. It
reports the status of the WP pin.
Bit 2 (CISWP) reflects whether the Common
Memory CIS is write protected using the write
protect register, with 1 indicating write protected.
Bit 3 (RP) reports whether the entire flash memory
array is in deep-sleep (reset power-down) mode,
with 1 indicating deep-sleep. This bit reflects the RP
bit of the global reset power-down register.
Powering down
all
device pairs individually (using
the sleep control register), also sets this bit.
Bit 4 (CMWP) reports whether the Common
Memory Plane (minus Common Memory CIS) is
write protected via the write protect register with 1
indicating write protected.
Bit 5 (SRESET) reflects the SRESET bit of the soft
reset register. It reports that the card is in Soft
Reset with 1 indicating reset. When this bit is zero,
the flash memory array and CMRs may be
accessed, otherwise clear it via the SRESET
register.
Bit 6 (ADS, Any Device Sleep) is the “ORed” value
of the sleep control register. Powering down any
device pair sets this bit.
Bit 7 (ADM, Any Device Masked) is the “ORed”
value of the ready/busy mask register. Masking any
device sets this bit.
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