- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377495 > iMC010FLSA (Intel Corp.) 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲器卡) PDF資料下載
參數(shù)資料
| 型號： | iMC010FLSA |
| 廠商： | Intel Corp. |
| 英文描述： | 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲器卡) |
| 中文描述： | 5伏2系列閃存卡（5V的系列2閃速存儲器卡） |
| 文件頁數(shù)： | 23/51頁 |
| 文件大?。?/td> | 827K |
| 代理商： | IMC010FLSA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
E
15.0
iMC002/004/010/020FLSA
23
PRELIMINARY
COMMAND DEFINITIONS
15.1
Read Array (FFH)
Upon initial card power-up, after exit from the deep-
sleep modes, and whenever illegal commands are
given, individual devices default to the read array
mode. This mode is also entered by writing FFH
into the CUI. In this mode, microprocessor read
cycles retrieve array data. Devices remain enabled
for reads until the CUI receives an alternate
command. Once the internal WSM has started a
block-erase or data-write operation within a device,
that device will not recognize the Read Array
command until the WSM has completed its
operation (or the Erase Suspend command is
issued during erase).
15.2
Intelligent Identifier (90H)
After executing this command, the intelligent
identifier values can be read. Only address A
0
of
each device is used in this mode, all other address
inputs are reserved and should be cleared to 0.
[(Manufacturer code = 89H for A
0
= 0), (Device
code = A2H for A
0
= 1)]. The device will remain in
this mode until the CUI receives another command.
This information is useful by system software in
determining what type of flash memory device is
contained within the card and allows the correct
matching of device to write and erase algorithms.
System software that fully utilizes the PCMCIA
specification will not use the intelligent identifier
mode, as this data is available within the Card
Information Structure (refer to section on PCMCIA
Card Information Structure).
15.3
Read Status Register (70H)
After writing this command, a device read outputs
the contents of its status register, regardless of the
address presented to that device. The contents of
this register are latched on the falling edge of OE#,
CE
1
# (and/or CE
2
#), whichever occurs last in the
read cycle. This prevents possible bus errors which
might occur if the contents of the status register
changed while reading its contents. CE
1
# (and
CE
2
# for odd-byte or word access) or OE# must be
toggled with each subsequent status read, or the
completion of a write or erase operation will not be
evident. This command is executable while the
WSM is operating, however, during a block-erase or
data-write operation, reads from the device will
automatically return status register data. Upon
completion of that operation, the device remains in
the status register read mode until the CUI receives
another command.
The read status register command functions when
V
PP
= V
PPL
or V
PPH
.
15.4
Clear Status Register (50H)
The erase status and write status bits may be set to
“1”s by the WSM and can only be reset by the Clear
Status Register command. These bits indicate
various failure conditions. By allowing system
software to control the resetting of these bits,
several operations may be performed (such as
cumulatively writing several bytes or erasing
multiple blocks in sequence). The device’s status
register may then be polled to determine if an error
occurred during that sequence. This adds flexibility
to the way the device may be used.
Additionally, the V
PP
status bit (SR.3) MUST be
reset by system software (Clear Status Register
command)
before
further
attempted (after an error).
block-erases
are
The Clear Status Register command functions
when V
PP
= V
PPL
or V
PPH
. This command puts the
device in the read array mode.
15.5
Write Setup/Write
A two-command sequence executes a data-write
operation. After the system switches V
PP
to V
PPH
,
the write setup command (40H) is written to the CUI
of the appropriate device, followed by a second
write specifying the address and write data (latched
on the rising edge of WE#). The device’s WSM
controls the data-write and write verify algorithms
internally. After receiving the two-command write
sequence, the device automatically outputs status
register data when read (see Figure 13). The CPU
detects the completion of the write operation by
analyzing card-level or device-level indicators.
Card-level indicators include the RDY/BSY# pin and
the ready-busy status register; while device-level
indicators include the specific device’s status
register. Only the Read Status Register command
is valid while the write operation is active. Upon
completion of the data-write sequence (see section
on status register) the device’s status register
reflects
the
result
of
the
write
operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| iMC020FLSA | 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲器卡) |
| IMC004FLSA | SERIES 2 FLASH MEMORY CARDS iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA |
| IMC004FLSC | 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲器卡) |
| IMC008FLSC | 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲器卡) |
| IMC016FLSC | 5 V Value Series 100 Flash Memory Card(5V 100系列閃速存儲器卡) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IMC010FLSAET | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8/x16 Flash EEPROM Module |
| IMC01GR | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:IM Series Signal Relays |
| IMC01TS | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:IM Series Signal Relays |
| IMC02 | 制造商:TE Connectivity 功能描述:PROTECTIVE CABLE CLIP CLIP-ON 制造商:TE Connectivity 功能描述:IMC MARKER CLIP SIZE 02 |
| IMC020FLSA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SERIES 2 FLASH MEMORY CARDS iMC002FLSA, iMC004FLSA, iMC010FLSA, iMC020FLSA |
發(fā)布緊急采購，3分鐘左右您將得到回復。