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參數(shù)資料
| 型號： | iMC010FLSA |
| 廠商： | Intel Corp. |
| 英文描述： | 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲器卡) |
| 中文描述： | 5伏2系列閃存卡（5V的系列2閃速存儲器卡） |
| 文件頁數(shù)： | 24/51頁 |
| 文件大小： | 827K |
| 代理商： | IMC010FLSA |
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iMC002/004/010/020FLSA
E
24
PRELIMINARY
The device remains in the read status register
mode until the CUI receives an alternate command.
15.6
Erase Setup/Erase Confirm
Commands (20H)
Within a device, a two-command sequence initiates
an erase operation on one device block at a time.
After the system switches V
PP
to V
PPH
, an Erase
Setup command (20H) prepares the CUI for the
Erase Confirm command (D0H). The device’s WSM
controls the erase algorithms internally. After
receiving the two-command erase sequence, the
device automatically outputs status register data
when read (see Figure 14). If the command after
erase setup is not an Erase Confirm command, the
CR sets the write railure and erase failure bits of the
status register, places the device into the read
status register mode, and waits for another
command. The Erase Confirm command enables
the WSM for erase (simultaneously closing the
address latches for that device’s block (A
16
–A
19
).
The CPU detects the completion of the erase
operation by analyzing card-level or device-level
indicators.
Card-level
RDY/BSY pin and the ready-busy status register;
while device-level indicators include the specific
device’s status register. Only the Read Status
Register and Erase Suspend command is valid
during an active erase operation. Upon completion
of the erase sequence (see section on status
register) the device’s status register reflects the
result of the erase operation. The device remains in
the read status register mode until the CUI receives
an alternate command.
indicators
include
the
The two-step block-erase sequence ensures that
memory contents are not accidentally erased.
Erase attempts while V
PPL
< V
PP
< V
PPH
produce
spurious results and are not recommended.
Reliable block erasure only occurs when V
PP
=
V
PPH
. In the absence of this voltage, memory
contents are protected against erasure. If block
erase is attempted while V
PP
= V
PPL
, the V
PP
status
bit will be set to “1.”
When erase completes, the erase status bit should
be checked. If an erase error is detected, the
device’s status register should be cleared. The CUI
remains in read status register mode until receiving
an alternate command.
15.7
Erase Suspend (B0H)/Erase
Resume (D0H)
Erase Suspend allows block erase interruption to
read data from another block of the device or to
temporarily conserve power for another system
operation. Once the erase process starts, writing
the Erase Suspend command to the CUI (see
Figure 15) requests the WSM to suspend the erase
sequence at a predetermined point in the erase
algorithm. In the erase suspend state, the device
continues to output status register data when read.
Polling the device’s RY/BY# and erase suspend
status bits (status register) will determine when the
erase suspend mode is valid. It is important to note
that the card’s RDY/BSY# pin will also transition to
V
OH
and will generate an interrupt if this pin is
connected to a system-level interrupt. At this point,
a Read Array command can be written to the
device’s CUI to read data from blocks
other than
those which are suspended
. The only other valid
commands at this time are read status register
(70H) and Erase Resume (D0H). If V
PP
goes low
during Erase Suspend, the V
PP
status bit is set in
the status register and the erase operation is
aborted.
The Erase Resume command clears the Erase
suspend state and allows the WSM to continue with
the erase operation. The device’s RY/BY# status
and erase suspend status bits and the card’s ready-
busy status register are automatically updated to
reflect the erase resume condition. The card’s
RDY/BSY# pin also returns to V
OL
.
15.8
Invalid/Reserved
These are unassigned commands having the same
effect as the Read Array command. Do not issue
any command other than the valid commands
specified above. Intel reserves the right to redefine
these codes for future functions.
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