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參數(shù)資料
| 型號： | iMC010FLSA |
| 廠商： | Intel Corp. |
| 英文描述： | 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲器卡) |
| 中文描述： | 5伏2系列閃存卡（5V的系列2閃速存儲器卡） |
| 文件頁數(shù)： | 27/51頁 |
| 文件大小： | 827K |
| 代理商： | IMC010FLSA |
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E
iMC002/004/010/020FLSA
27
PRELIMINARY
Start
Write Erase Setup
(1)
Command
Write Erase Confirm
Command
Read Status Register
(2)
Erase
Done
Full Status
(3)
Check if Desired
Block Erase
(4)
Completed
FULL STATUS CHECK PROCEDURE
Yes
No
Read Status Register
Data (See Above)
Voltage Range Error
(5)
Cmd Sequence Error
V
PP
Level OK
Cmd Sequence
OK
No
Yes
No
Yes
Block Erase
Successful
Suspend
Erase
Suspend
Erase
Loop
Yes
No
Command
Erase
Erase Setup
Defaults to
Device Status
Register Read
Mode
Command
Block Erase Error
(6)
Block Erase OK
No
Bus
Operation
Write
Write
Read
Standby
Bus
Operation
Standby
Standby
Standby
x8 Mode
Check SR Bit 3
1 = V
PP
Detected
Low
Check SR Bit 5
1 = Blk Erase Error
Check SR Bits
4 and 5
Both 1 =
Comd Seq Error
x16 Mode
Check SR Bits
3 and 11
Either Bit 1=
V
PP
Detected Low
Check SR Bits
5 and 13
Both 1 =
Blk Erase Failure
Check SR Bits
4, 5, 12, 13
All 1 =
Comd Seq Error
Data = 20H
Address = Block
Within Card to Be
Erased
x8 Mode
Data = D0H
Address = Block
Within Card to Be
Erased
Status Register
Data. Toggle OE#,
CE
# or CE
# to
Update Status
Register
Check SR Bit 7
1 = Ready
2 = Busy
x16 Mode
Data = 2020H
Address = Blk Pair
Within Card to Be
Erased
Status Register
Data. Toggle OE#,
(CE
# or CE
2
#) to
Update Status
Registers
Check SR Bits
7 and 15
1 = Ready
2 = Busy
Data = D0D0H
Address = Blk Pair
Within Card to Be
Erased
FIG14
NOTES:
1.
2.
3.
4.
5.
Repeat for subsequent data writes.
In addition, the card’s ready-busy status register or the RDY/BSY# pin may be used.
Full device-level status check can be done after each block erase or after a sequence of block erases.
Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to ready array mode.
If a block erase operation fails due to a low V
PP
(setting SR Bit 3), the Clear Status Register command
must
be issued
before further attempts are allowed by the Write State Machine.
If a block erase operation fails during a multiple block erase sequence, SR Bit 4 (Write Status) will not be cleared until the
Command User Interface receives the Clear Status Register command.
6.
Figure 14. Device-Level Automated Erase Algorithm
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