參數(shù)資料
型號(hào)： iMC010FLSA
廠商： Intel Corp.
英文描述： 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲(chǔ)器卡)
中文描述： 5伏2系列閃存卡（5V的系列2閃速存儲(chǔ)器卡）
文件頁數(shù)： 29/51頁
文件大小： 827K
代理商： IMC010FLSA
E
17.2
iMC002/004/010/020FLSA
29
PRELIMINARY
Sleep Mode
Writing a
“1” to the PWRDWN bit of the global
power-down register places all FlashFile memory
devices into a deep-sleep mode. This disables most
of the 28F008SA’s circuitry and reduces current
consumption to 0.2 μA per device. Additionally,
when the host system pulls ASIC control logic high
and latches all address and data lines (i.e., not
toggling), the card’s total current draw is reduced to
approximately 5 μA (CMOS input levels) for a
20-MB card. On writing a “0” to the PWRDWN bit
(global power-down register) or any individual
device pair (sleep control register), a deep-sleep
mode recovery period must be allowed for
28F008SA device circuitry to power back on.
18.0
SYSTEM DESIGN
CONSIDERATIONS
18.1
Power Supply Decoupling
Flash memory power-switching characteristics
require
careful
device
designers are interested in three supply current
issues—standby, active and transient current
peaks, produced by rising and falling edges of CE
1
#
and CE
2
#. The capacitive and inductive loads on
the card and internal flash memory device pairs
determine the magnitudes of these peaks.
decoupling.
System
The flash memory card features on-card ceramic
decoupling capacitors connected between V
CC
and
GND, and between V
PP1
/V
PP2
and GND to help
transient voltage peaks.
On the host side, the card connector should also
have a 4.7 μF electrolytic capacitor between V
CC
and GND, as well as between V
PP1
/V
PP2
and GND.
The bulk capacitors will overcome voltage slumps
caused by printed-circuit-board trace inductance,
and will supply charge to the smaller capacitors as
needed.
19.0
POWER UP/DOWN PROTECTION
Each device in the flash memory card is designed
to offer protection against accidental erasure or
writing, caused by spurious system-level signals
that may exist during power transitions. The card
will power-up into the read array mode.
A system designer must guard against active writes
for V
CC
voltages above V
LKO
when V
PP
is active.
Since both WE# and CE
1
# (and/or CE
2
#) must be
low for a command write, driving either to V
IH
will
inhibit writes. With its CUI, alteration of device
contents only occurs after successful completion of
the two-step command sequences.
While these precautions are sufficient for most
applications, an alternative approach would allow
V
CC
to reach its steady state value before raising
V
PP1
/V
PP2
above V
CC
+ 2.0 V. In addition, upon
powering-down, V
PP1
/V
PP2
should be below V
CC
+
2.0 V, before lowering V
CC
.
20.0
HOT INSERTION/REMOVAL
The capability to remove or insert PC cards while
the
system
is
powered
insertion/removal)
requires
approaches on the system and card levels. To
design for this capability consider card overvoltage
stress, system power droop and control line
stability.
on
careful
(i.e.,
hot
design
A
sequences the power supplies to the flash memory
card via shorter and longer pins. This assures that
hot insertion and removal will not result in card
damage or data loss.
PCMCIA/JEIDA
specified
socket
properly
21.0
PCMCIA CARD INFORMATION
STRUCTURE
The Card Information Structure (CIS) starts at
address zero of the card’s Attribute Memory Plane.
It contains a variable-length chain of data blocks
(tuples) that conform to a basic format as shown in
Table 5. This section describes each tuple
contained within the Series 2 Flash Memory Card.
21.1
The Device Information Tuple
This
information pertaining to the card’s speed and size.
The Series 2 Card is offered with a 150
nanosecond access time. Card sizes range
between 2 and 20 Megabytes.
tuple
(CISTPL_DEV
=
01H)
contains
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