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參數(shù)資料
| 型號： | iMC010FLSA |
| 廠商： | Intel Corp. |
| 英文描述： | 5 Volt Series 2 Flash Memory Card(5V系列2閃速存儲器卡) |
| 中文描述： | 5伏2系列閃存卡（5V的系列2閃速存儲器卡） |
| 文件頁數(shù)： | 21/51頁 |
| 文件大?。?/td> | 827K |
| 代理商： | IMC010FLSA |
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E
14.0
iMC002/004/010/020FLSA
21
PRELIMINARY
PRINCIPLES OF DEVICE
OPERATION
Individual 28F008SA devices include a Command
User Interface (CUI) and a Write State Machine
(WSM) to manage write and erase functions in each
device block.
The CUI serves as the device’s interface to the
Card Control Logic by directing commands to the
appropriate device circuitry (Table 4). It allows for
fixed power supplies during block erasure and data
writes. The CUI handles the WE# interface into the
device data and address latches, as well as system
software requests for status while the WSM is
operating.
The CUI itself does not occupy an addressable
memory location. The CUI provides a latch used to
store the command and address and data
information needed to execute the command. Erase
Setup and Erase Confirm commands require both
appropriate command data and an address within
the block to be erased. The Data Write Setup
command requires both appropriate command data
and the address of the location to be written, while
the Data Write command consists of the data to be
written and the address of the location to be written.
The CUI initiates flash memory writing and erasing
operations only when V
PP
is at 12 V. Depending on
the application, the system designer may choose to
make the V
PP
power supply switchable (available
when writes and erases are required) or hardwired
to V
PPH
. When V
PP
= V
PPL
, power savings are
incurred and memory contents cannot be altered.
The CUI architecture provides protection from
unwanted write and erase operations even when
high voltage is applied to V
PP
. Additionally, all
functions are disabled whenever V
CC
is below the
write lockout voltage V
LKO
, or when the card’s
deep-sleep modes are enabled. The WSM
automates the writing and erasure of blocks within a
device. This on-chip state machine controls block
erase and data-write, freeing the host processor for
other tasks. After receiving the Erase Setup and
Erase Confirm commands from the CUI, the WSM
controls block-erase. Progress is monitored via the
device’s status register, the card’s control logic, and
the RDY/BSY# pin of the PCMCIA interface. Data-
write is similarly controlled, after destination
address and expected data are supplied.
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