參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁數(shù)： 7/98頁
文件大?。?/td> 601K
代理商： IDT88P8344
7
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
List of Tables (Continued)
Table 112 - SPI-4 ingress bit alignment counter register (0x02 to 0x0B) .........................................................................................................................75
Table 113 - SPI-4 ingress manual alignment phase/result register (0x0C to 0x1F)..........................................................................................................75
Table 114 - SPI-4 Egress data lane timng register (register_offset 0x2A)........................................................................................................................75
Table 115 - SPI-4 egress Control Lane Timng register (Register_offset 0x2B) ...............................................................................................................76
Table 116 - SPI-4 egress data clock timng register (register_offset 0x2C).......................................................................................................................76
Table 117 - SPI-4 egress status timng register (register_offset 0x2D) ............................................................................................................................76
Table 118 - SPI-4 egress status clock timng register (register_offset 0x2E) ....................................................................................................................76
Table 119 - PMON timebase control register (register_offset 0x00) .................................................................................................................................77
Table 120 - Timebase register (register_offset 0x01)......................................................................................................................................................77
Table 121 - Clock generator control register (register_offset 0x10) .................................................................................................................................77
Table 122 - OCLK and MCLK frequency select encoding...............................................................................................................................................77
Table 123 - GPIO register (register_offset 0x20) ............................................................................................................................................................78
Table 124 - GPIO monitor table (5 entries 0x21-0x25 for GPIO[0] through GPIO[4]).......................................................................................................78
Table 125 - Version number register (register_offset 0x30).............................................................................................................................................78
Table 126 – JTAG instructions........................................................................................................................................................................................79
Table 127 – Absolute maximumratings...........................................................................................................................................................................79
Table 128 – Recommended Operating Conditions..........................................................................................................................................................79
Table 129 – Termnal Capacitance.................................................................................................................................................................................80
Table 130 – Thermal Characteristics..............................................................................................................................................................................80
Table 131 – DC Electrical characteristics........................................................................................................................................................................81
Table 132 – SPI-3 AC Input / Output timng specifications ................................................................................................................................................82
Table 133 – SPI-4.2 LVDS AC Input / Output timng specifications....................................................................................................................................84
Table 134 – SPI-4 LVTTL status AC Characteristics .......................................................................................................................................................84
Table 135 – REF_CLK clock input.................................................................................................................................................................................84
Table 136 – OCLK[3:0] clock outputs and MCLK internal clock.......................................................................................................................................84
Table 137 – Mcroprocessor interface ............................................................................................................................................................................84
Table 138 – Mcroprocessor parallel port Motorola read timng.......................................................................................................................................85
Table 139 – Mcroprocessor parallel port Motorola write timng.......................................................................................................................................86
Table 140 – Mcroprocessor parallel port Intel mode read timng.....................................................................................................................................87
Table 141 – Mcroprocessor parallel port Intel mode write timng.....................................................................................................................................88
Table 142 – Mcroprocessor serial peripheral interface timng.........................................................................................................................................89
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