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參數(shù)資料
| 型號： | IDT88P8344 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPI交換4 ×的SPI - 3至SPI - 4期1.0 |
| 文件頁數(shù)： | 12/98頁 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344 |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Name
I/O type
Parallel microprocessor
pin used
WRB
DBUS[0]
CSB
RDB
----------
----------
Serial Peripheral Interface Pin Use Description
SDI
SDO
CSB
SCLK
INTB
SPI_EN
I-ST CMOS
B-PU CMOS
I-ST CMOS
I-ST CMOS
OD CMOS
I-PU CMOS
Serial data in, rise edge sampling
Serial data out, falling edge driving
Chip select, active low. SDO is tri-stated when CSB is high
Input clock
Interrupt, active low, open drain
Dedicated input. High selects SPI mcroprocessor interface (internally pulled up)
TABLE 9 – MISCELLANEOUS
Name
REF_CLK
OCLK[3:0]
CLK_SEL[3:0] I-PU CMOS
TIMEBASE
GPIO[4:0]
TDI
TDO
TCK
TMS
TRSTB
RESETB
I/O type
I-ST CMOS
O LVTTL
Description
Master clock input
Clock outputs that can be used for SPI-3, phase-shifted to avoid simultaneously switching outputs
Clock select inputs for internal PLL, internal MCLK, and OCLK[3:0] outputs
Timeout signal for counters
General purpose I/O or internal state monitor pins
JTAG data in (internally pulled up)
JTAG data out
JTAG clock
JTAG mode (internally pulled up)
JTAG reset, active low (internally pulled up). Pull down for normal operation.
Master hardware reset, active low
B-PU CMOS
B-PU CMOS
I-PU CMOS
O-Z CMOS
I-ST CMOS
I-PU CMOS
I-PU CMOS
I-PD CMOS
NOTE
:
1. Inputs with internal pull-ups do not need external pull-ups unless connected to PCB trace (except TRSTB).
Parallel microprocessor Interface
The Parallel mcroprocessor interface is configurable to work in Intel or Motorola modes. Be sure to connect SPI_EN to a logic low when
using the parallel mcroprocessor interface mode.
Name
MPM
CSB
RDB
I/O type
I-PU CMOS Mcroprocessor mode: 0=Motorola Mode, 1=Intel mode (sampled after reset)
I-ST CMOS
Chip select; active low
I-ST CMOS
RDB: Read control, active low (in Intel mode), or
DSB: Data strobe, active low (in Motorola mode)
I-ST CMOS
WRB: Write control; active low; (in Intel mode), or
R/WB: Read/write control; when high, read is active; when low, write is active; (in Motorola mode)
I-PU CMOS Address bus
B-PU CMOS Data bus
OD CMOS
Interrupt, active low, open drain
I-PU CMOS Logic low selects parallel mcroprocessor interface (internally pulled up, sampled after reset)
Description
WRB
ADD[5:0]
DBUS[7:0]
INTB
SPI_EN
TABLE 7 – PARALLEL MICROPROCESSOR INTERFACE
TABLE 8 – SERIAL MICROPROCESSOR INTERFACE (SERIAL PERIPHERAL INTERFACE MODE)
Four pins multiplexed with parallel mcroprocessor pins. Be sure to connect SPI_EN to a logic high when using the serial mcroprocessor
interface mode.
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| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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