參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁(yè)數(shù)： 4/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344
4
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
List of Figures
Figure 1. Typical application: NPU, PHY, and co-processor.............................................................................................................................................8
Figure 2. Data path diagram............................................................................................................................................................................................8
Figure 3. Link mode SPI-3 ingress interface...................................................................................................................................................................14
Figure 4. PHY mode SPI-3 ingress interface..................................................................................................................................................................14
Figure 5. Link mode SPI-3 egress interface....................................................................................................................................................................16
Figure 6. PHY mode SPI-3 egress interface...................................................................................................................................................................16
Figure 7. Data sampling diagram...................................................................................................................................................................................18
Figure 8. SPI-4 ingress state diagram............................................................................................................................................................................19
Figure 9. SPI-4 egress status state diagram...................................................................................................................................................................21
Figure 10. Interrupt scheme...........................................................................................................................................................................................22
Figure 11. Definition of data flows ...................................................................................................................................................................................23
Figure 12. Logical view of datapath configuration using PFPs.........................................................................................................................................24
Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor.............................................................................................................................25
Figure 14. SPI-3 ingress LP to LID map........................................................................................................................................................................27
Figure 15. SPI-4 egress LID to LP map.........................................................................................................................................................................28
Figure 16. SPI-3 ingress to SPI-4 egress datapath........................................................................................................................................................28
Figure 17. SPI-3 ingress to SPI-4 egress flow control path.............................................................................................................................................29
Figure 18. SPI-4 ingress to SPI-3 egress packet fragment processor.............................................................................................................................30
Figure 19. SPI-4 ingress to SPI-3 egress datapath........................................................................................................................................................31
Figure 20. SPI-4 ingress to SPI-3 egress flow control.....................................................................................................................................................32
Figure 21. SPI-3 ingress to SPI-3 egress datapath........................................................................................................................................................33
Figure 22 . Mcroprocessor data capture buffer..............................................................................................................................................................34
Figure 23. SPI-3 ingress to mcroprocessor capture interface datapath...........................................................................................................................34
Figure 25. Mcroprocessor interface to SPI-3 egress detailed datapath diagram..............................................................................................................35
Figure 24 . Mcroprocessor data insert buffer.................................................................................................................................................................35
Figure 26. Mcroprocessor data insert buffer..................................................................................................................................................................36
Figure 27. Mcroprocessor data insert interface to SPI-4 egress datapath.......................................................................................................................36
Figure 28. Mcroprocessor data capture buffer...............................................................................................................................................................37
Figure 29. SPI-4 ingress to mcroprocessor data capture interface path..........................................................................................................................37
Figure 30. Clock generator............................................................................................................................................................................................39
Figure 31. SPI-3 Loopback diagram..............................................................................................................................................................................40
Figure 32. Power-on-Reset Sequence..........................................................................................................................................................................41
Figure 33. DDR interface and eye opening check through over sampling.......................................................................................................................44
Figure 34. Direct & indirect access.................................................................................................................................................................................46
Figure 35. SPI-3 I/O timng diagram...............................................................................................................................................................................82
Figure 36. SPI-4 I/O timng diagram...............................................................................................................................................................................83
Figure 37. Mcroprocessor parallel port Motorola read timng diagram............................................................................................................................85
Figure 38. Mcroprocessor parallel port Motorola write timng diagram............................................................................................................................86
Figure 39. Mcroprocessor parallel port Intel mode read timng diagram..........................................................................................................................87
Figure 40. Mcroprocessor parallel port Intel mode write timng diagram..........................................................................................................................88
Figure 41. Mcroprocessor serial peripheral interface timng diagram..............................................................................................................................89
Figure 42. IDT88P8344 820PBGA package, bottomview..............................................................................................................................................94
Figure 43. IDT88P8344 820PBGA package, top and side views....................................................................................................................................95
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