參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁(yè)數(shù)： 62/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344
62
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Non LID associated interrupt indication register
(Block_base 0x0C00 + Register_offset 0x0C)
TABLE 62 - NON LID ASSOCIATED INTERRUPT
INDICATION REGISTER (REGISTER_OFFSET
0x0C)
Field
Bits
0
1
2
3
4
31:5
Length
1
1
1
1
1
27
Initial Value
0b0
0b0
0b0
0b0
0b0
0x0
SPI4_LOCK_UN
SPI3_LOCK_UN
SPI3_ICLK_UN
SPI3_ECLK_UN
SPI3_FLUSH
Reserved
The Non LID associated interrupt indication register is at Block_Base
0x0C00. The Non LID interrupt indication register is used to determne the status
of SPI-3 and SPI-4 port interrupts. The Non LID associated interrupt indication
register is read and subsequently a “1” is written to acknowledge individual
interrupts in this register. An interrupt is generated when enabled by the
corresponding enable flag in the Non LID associated interrupt indication
register. The bit fields in the Non LID associated interrupt indication register are
described.
SPI4_LOCK_UN
The SPI-4 interface can create an event indicating that
the SPI-4 ingress has dropped data due the unavailability of ingress buffering.
0=No operation
1=The SPI-4 interface has dropped data due the
unavailability of ingress buffering.
SPI3_LOCK_UN
A SPI-3 interface can create an event indicating that a
SPI-3 ingress has dropped data due the unavailability of ingress buffering.
0=No operation
1=A SPI-3 interface has dropped data due the
unavailability of ingress buffering.
SPI3_ICLK_UN
SPI-3 ingress clock has failed. No transitions were detected on a SPI-3 ingress
clock (I_FCLK)
0=No operation
1=A SPI-3 ingress clock has failed.
A SPI-3 interface can create an event indicating that a
SPI3_ECLK_UN
A SPI-3 interface can create an event indicating that a
SPI-3 egress clock has failed. No transitions were detected on a SPI-3 egress
clock (E_FCLK)
0=No operation
1=A SPI-3 egress clock has failed.
SPI3_FLUSH
SPI-3 buffer has been flushed and data has been lost. A buffer is flushed if an
address parity error is detected, or if an ingress buffer is not available at the time
it is requested.
0=No operation
1=A SPI-3 buffer has been flushed.
A SPI-3 interface can create an event indicating that a
Non LID associated interrupt enable register
(Block_base 0x0C00 + Register_offset 0x0D)
TABLE 63 - NON LID ASSOCIATED INTERRUPT
ENABLE REGISTER(REGISTER_OFFSET 0x0D)
Field
Bits
SPI4_LOCK_UN
0
SPI3_LOCK_UN
1
SPI3_ICLK_UN
2
SPI3_ECLK_UN
3
SPI3_FLUSH
4
Reserved
31:5
Length
1
1
1
1
1
27
Initial Value
0b0
0b0
0b0
0b0
0b0
0x0000
The Non LID associated interrupt enable register is at Block_Base 0x0C00
+ Register_offset 0x0D. The Non LID associated interrupt enable register is
used to mask the status of SPI-3 and SPI-4 port interrupts in the Non LID
associated interrupt indication register. The Non LID associated interrupt enable
register has read and write access. The bit fields in the Non LID associated
interrupt enable register are active “1” interrupt enables for the corresponding
bit fields in the Non LID associated interrupt indication register.
LID associated interrupt indication register
(Block_base 0x0C00 + Register_offset 0x0E)
TABLE 64 - LID ASSOCIATED INTERRUPT INDICA-
TION REGISTER (REGISTER_OFFSET 0x0E)
Field
Bits
EVENT_TYPE
5:0
Reserved
31:6
Length
6
26
Initial Value
0x00
0x0
The LID associated interrupt indication register is at Block_Base 0x0C00 +
Register_offset 0x0E. The LID associated interrupt indication register is used
to determne the EVENT_TYPE of SPI-3 and SPI-4 interrupts. The
EVENT_TYPE coding is given in the Table 66 - Non critical LID associated
capture table (0x10-0x15). The LID associated interrupt indication register is
read and subsequently a 0xFF must be written for interrupt acknowledge. An
EVENT_TYPE interrupt is generated when enabled by the EVENT_TYPE
enable flag in the LID associated interrupt enable register.
LID associated interrupt enable register
(Block_base 0x0C00 + Register_offset 0x0F)
TABLE 65 - LID ASSOCIATED INTERRUPT ENABLE
REGISTER (REGISTER_OFFSET 0x0F)
Field
Bits
EVENT_TYPE
5:0
Reserved
31:6
The LID associated interrupt enable register is at Block_Base 0x0C00 +
Register_offset 0x0F. The LID associated interrupt enable register is used to
mask the EVENT_TYPE of SPI-3 and SPI-4 per-LID interrupts. The LID
associated interrupt enable register has read and write access.
Length
6
26
Initial Value
0x00
0x0
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