參數(shù)資料
型號(hào)： IDT88P8344BHGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝： GREEN, PLASTIC, BGA-820
文件頁(yè)數(shù)： 1/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344BHGI
1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6370/7
APRIL 2006
SPI EXCHANGE 4 x SPI-3 TO SPI-4
Issue 1.0
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
INDUSTRIAL TEMPERATURE RANGE
IDT88P8344
HIGH LEVEL FUNCTIONAL BLOCK DIAGRAM
6370 drw01
SPI-3 A
64 Logical Ports
SPI-3 B
64 Logical Ports
SPI-3 C
64 Logical Ports
SPI-3 D
64 Logical Ports
JTAG IF
Control Path
Data Path
Uproc IF
Clock Generator
PFP = Packet Fragment Processor
SPI-4
256
Logical
Ports
SPI-4 to SPI-3 PFP
SPI-3 to SPI-4 PFP
SPI-3 to SPI-4 PFP
SPI-4 to SPI-3 PFP
SPI-3 to SPI-4 PFP
SPI-4 to SPI-3 PFP
SPI-3 to SPI-4 PFP
SPI-4 to SPI-3 PFP
FEATURES
Functionality
-
Low speed to high speed SPI exchange device
-
Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction
-
Per LP configurable memory allocation
-
Maskable interrupts for fatal errors
-
Fragment and burst length configurable per interface: mn 16 bytes,
max 256 bytes
Standard Interfaces
-
Four OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64
concurrently active LPs per interface
- One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256
concurrently active LPs
- SPI-4 FIFO status channel options:
LVDS full-rate
LVTTL eighth-rate
- Compatible with Network Processor Streamng Interface (NPSI)
NPE-Framer mode of operation
- SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the
entire frequency range
- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle
- IEEE 1149.1 JTAG
- Serial or parallel mcroprocessor interface for control and monitoring
Full Suite of Performance Monitoring Counters
-
Number of packets
-
Number of fragments
-
Number of errors
-
Number of bytes
Green parts available, see ordering information
APPLICATIONS
Ethernet transport
SONET / SDH packet transport line cards
Broadband aggregation
Multi-service switches
IP services equipment
DESCRIPTION
The IDT88P8344 is a SPI (SystemPacket Interface) Exchange with four SPI-
3 interfaces and one SPI-4 interface. The data that enter on the low speed
interface (SPI-3) are mapped to logical identifiers (LIDs) and enqueued for
transmssion over the high speed interface (SPI-4). The data that enter on the
high speed interface (SPI-4) are mapped to logical identifiers (LIDs) and
enqueued for transmssion over a low speed interface (SPI-3). A data flow
between SPI-3 and SPI-4 interfaces is accomplished with LID maps. The logical
port addresses and number of entries in the LID maps may be dynamcally
configured. Various parameters of a data flow may be configured by the user
such as buffer memory size and watermarks. In a typical application, the
IDT88P8344 enables connection of multiple SPI-3 devices to a SPI-4 network
processor. In other applications SPI-3 or SPI-4 devices may be connected to
multiple SPI-3 network processors or traffic managers.
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