參數(shù)資料
型號(hào)： IDT88P8344
廠商： Integrated Device Technology, Inc.
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPI交換4 ×的SPI - 3至SPI - 4期1.0
文件頁(yè)數(shù)： 6/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344
6
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
List of Tables (Continued)
Table 57 - SPI-3 egress test register (register_offset=0x02)............................................................................................................................................59
Table 58 - SPI-3 egress fill level register (register_offset=0x03)......................................................................................................................................60
Table 59 - SPI-3 egress max fill level register (register_offset=0x04) ..............................................................................................................................60
Table 60 - LID associated event counters (0x000-0x17F)..............................................................................................................................................61
Table 61 - Non LID associated event counters (0x00 - 0x0B) ........................................................................................................................................61
Table 62 - Non LID associated interrupt indication register (register_offset 0x0c).............................................................................................................62
Table 63 - Non LID associated interrupt enable register(register_offset 0x0D) ................................................................................................................62
Table 64 - LID associated interrupt indication register (register_offset 0x0E)....................................................................................................................62
Table 65 - LID associated interrupt enable register (register_offset 0x0F) .......................................................................................................................62
Table 66 - Non critical LID associated capture table (register_offset 0x10-0x15) .............................................................................................................63
Table 67 - SPI-3 to SPI-4 critical LID interrupt indication registers (register_offset 0x16-0x17).........................................................................................63
Table 68 - SPI-3 to SPI-4 critical LID interrupt enable registers (register_offset 0x18-0x19) ............................................................................................63
Table 69 - SPI-4 to SPI-3 critical LID interrupt indication registers (register_offset 0x1A-0x1B) ........................................................................................63
Table 70 - SPI-4 to SPI-3 critical LID interrupt enable registers (register_offset 0x1C-0x1D) ...........................................................................................63
Table 71 - Critical events source indication register (register_offset 0x1E).......................................................................................................................63
Table 72 - SPI-3 ingress packet length configuration register..........................................................................................................................................64
Table 73 - SPI-4 egress port descriptor table (64 entries)...............................................................................................................................................64
Table 74 - SPI-4 egress DIRECTION code assignment.................................................................................................................................................64
Table 75 - SPI-3 ingress port descriptor table (Block_base 0x1200 + Register_offset 0x00-0x3F) ..................................................................................64
Table 76 - SPI-3 to SPI-4 PFP register (register_offset 0x00).........................................................................................................................................65
Table 77 - NR_LID field encoding..................................................................................................................................................................................65
Table 78 - SPI-3 to SPI-4 flow control register (register_offset 0x01)...............................................................................................................................65
Table 79 - SPI-4 ingress packet length configuration (64 entries)....................................................................................................................................66
Table 80 - SPI-3 egress port descriptor table (64 entries)..............................................................................................................................................66
Table 81 - SPI-3 egress DIRECTION code assignment.................................................................................................................................................66
Table 82 - SPI-4 ingress port descriptor table (64 entries)..............................................................................................................................................66
Table 83 - SPI-4 to SPI-3 PFP register (0x00)...............................................................................................................................................................67
Table 84 - NR_LID field encoding..................................................................................................................................................................................67
Table 85 -Common Module (Module_base 0x8000) indirect register table......................................................................................................................68
Table 86 - SPI-4 ingress LP to LID map (256 entries, one per LP).................................................................................................................................69
Table 87 - SPI-4 ingress calendar_0 (256 entries).........................................................................................................................................................69
Table 88 - SPI-4 ingress calendar_1 (256 entries).........................................................................................................................................................69
Table 89 - SPI-4 ingress configuration register (0x00)....................................................................................................................................................69
Table 90 - SPI-4 ingress status configuration register (register_offset 0x01) ....................................................................................................................70
Table 91 - SPI-4 ingress status register (register_offset 0x02) ........................................................................................................................................70
Table 92 - SPI-4 ingress inactive transfer port (register_offset 0x03)...............................................................................................................................70
Table 93 - SPI-4 ingress calendar configuration register (0x04 to 0x05).........................................................................................................................71
Table 94 – SPI-4 ingress watermark register (register_offset 0x06) ...............................................................................................................................71
Table 95 - SPI-4 ingress fill level register (0x07 to 0x0A) ..............................................................................................................................................71
Table 96 - SPI-4 ingress max fill level register (0x0B to 0x0E) ......................................................................................................................................71
Table 97 - SPI-4 ingress diagnostics register (register_offset 0x0F)................................................................................................................................71
Table 98 - SPI-4 ingress DIP-4 error counter (register_offset 0x10)..............................................................................................................................72
Table 99 - SPI-4 ingress bit alignment control register (register_offset 0x11)...................................................................................................................72
Table 100 - SPI-4 ingress start up training threshold register (register_offset 0x12)........................................................................................................72
Table 101 - SPI-4 egress LID to LP map (256 entries)...................................................................................................................................................72
Table 102 - SPI-4 egress calendar_0 (256 locations)....................................................................................................................................................72
Table 103 - SPI-4 egress calendar_1 (256 locations)....................................................................................................................................................73
Table 104 – SPI-4 egress configuration register_0 (register_offset 0x00)........................................................................................................................73
Table 105 - SPI-4 egress configuration register_1 (register_offset 0x01) ........................................................................................................................73
Table 106 - SPI-4 egress status register (register_offset 0x02) .......................................................................................................................................74
Table 107 - SPI-4 egress calendar configuration register (Register_offset 0x03 - 0x04)..................................................................................................74
Table 108 – SPI-4 egress diagnostics register (register_offset 0x05) ..............................................................................................................................74
Table 109 - SPI-4 egress DIP-2 error counter (register_offset 0x06).............................................................................................................................74
Table 110 - SPI-4 ingress bit alignment window register (register_offset 0x00)................................................................................................................75
Table 111 - SPI-4 ingress lane measure register (register_offset 0x01)..........................................................................................................................75
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