89
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
6370 drw11
SCLK
tCSH
High Impedance
Valid Input
tCLD
tCSD
tCLL
tCLH
tCSS
tDIS
tDIH
tPD
Valid Output
tDF
High Impedance
SDI
SDO
CSB
11.6.6.2 Serial microprocessor interface (serial
peripheral interface mode)
Timing Characteristics
The maximum SPI Data transfer clock frequency is 2 MHz. The detail
informationofthetimingcharacteristicsisshowninbelowandtimingdiagramis
showninFigure41,Microprocessorserialperipheralinterfacetimingdiagram.
Symbol
Description
Min.
Max.
Unit
fOP
SCLK Frequency
2.0
MHz
fCSH
Minimum CSB High Time
100
ns
tCSS
CSB Setup Time
50
ns
tCSD
CSB Hold Time
100
ns
tCLD
SCLK Clock Disable Time
50
ns
tCLH
SCLK Clock High Time
205
ns
tCLL
SCLK Clock Low Time
205
ns
tDIS
SDI Data Setup Time
50
ns
tDIH
SDI Data Hold Time
150
ns
tPD
SDO Output Delay
150
ns
tDF
SDO Output Disable Time
50
ns
Figure 41. Microprocessor serial peripheral interface timing diagram
TABLE 142 – MICROPROCESSOR SERIAL PERIPHERAL INTERFACE TIMING