- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1924 > IDT88P8342BHI (IDT, Integrated Device Technology Inc)IC SPI3-SPI4 EXCHANGE 820-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT88P8342BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 40/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8342BHI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
45
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Counter
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
Value
0
P
0
K
0
#define SPI-4_ingress_lane_measure_register 0x8801
/* register address in SPI exchange device*/
#define SPI-4_ingress_bit_alignment_counter_register(0) 0x8802
#define SPI-4_ingress_bit_alignment_counter_register(1) 0x8803
#define SPI-4_ingress_bit_alignment_counter_register(2) 0x8804
#define SPI-4_ingress_bit_alignment_counter_register(3) 0x8805
#define SPI-4_ingress_bit_alignment_counter_register(4) 0x8806
#define SPI-4_ingress_bit_alignment_counter_register(5) 0x8807
#define SPI-4_ingress_bit_alignment_counter_register(6) 0x8808
#define SPI-4_ingress_bit_alignment_counter_register(7) 0x8809
#define SPI-4_ingress_bit_alignment_counter_register(8) 0x880a
#define SPI-4_ingress_bit_alignment_counter_register(9) 0x880b
For lane=0 to K step 1
/*the number K depend on status mode: K=18 in LVDS status mode*/
{
/*
K=16otherwise */
write #lane, SPI-4_ingress_lane_measure_ register
wait until BUSY=0
/* BUSY: bit 8 of SPI-4_ingress_lane_measure_register, at address
0x8801*/
for i=0 to 9 step 1
{
read C(i), SPI-4_ingress_bit_alignment_counter_register(i)
}
print C(0), C(1), C(2), C(3), C(4), C(5), C(6), C(7), C(8), C(9)
}
For an ideal case, there is zero jitter on clock an data, zero skew, the clock
high and low level phase are symmetrical. For random input data on each lane,
the counters Cn=CNTn(t)+CNTn(t+1)+. . .+CNTn(t+T), where T is a time
window to do the statistics computation, will increment as follows:
Where P and K are non-zero and need to be a large enough value mark
the transition position of a clock and define the position.
Software for implementing the Eye-Opening Check
IntheIDT88P8342,asetofdiagnosticregistersareprovidedforimplement-
ing an eye-opening check. The SPI-4 interface has 16 data lanes and one
control lane on ingress, 2 status lanes on egress, making a total of 19 lanes.
TheSPI-4ingressbitalignmentwindowregisterdefinesthewindowTstated
above, based on which the signal statistics are computed. It is recommended
to use the default value. The MEASURE_BUSY bit indicates the status of the
internalmeasurementoperation.
The SPI-4 ingress lane measure register selects the lane statistics counters
to be read, a write to this register triggers the eye-opening check process to the
BecausetheSPI-4ingressbitalighnmentcounterregisterhasa10-bitwidth,
the maximum counter value is 0x3ff.
If the counter values of a lane are:
0, 0, 0x3ff, 0, 0, 0, 0, 0x3ff, 0, 0
The eye open is perfect; there is very good signal integrity on input signals
of the SPI-4 interface.
Ineachsamplepositionrepresentsa“tap”.Dependingonthedelayinalane,
even a small jitter value of 1ps on the lane or the clock, may cause eye closing
thatcanbedetectedbyobservingthecountervalues.Inanidealcasewithzero
selected lanes and the MEASURE_BUSY bit will be set accordingly indicating
themeasuringprocessisactive.TheMEASURE_BUSYbitisclearedinternally
which indicates that the measuring process is complete. The measured result
of counters C
0 through C9 will be available in the SPI-4 ingress bit alignment
counter registers.
Note that there is one SPI-4 ingress lane measure register and 19 SPI-4
ingress bit alignment counter registers.
The following pseudo code shows how to check the eye opening:
delay, if the jitter on a data lane or clock is less than one tap interval (peak to
peak), the jitter will not be reflected in counters. While the eye open check can
indicate excessive jitter there are limitations in providing a accurate measure-
mentusingthismethod.
Theoretically as long as one tap accumulates enough non-zero samples for
each 2 bits within a clock cycle the sampled signal position will be correct and
the interface will function correctly. The more counters that have zero values,
the better the eye opening.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT88P8344BHI | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| IDT89H24NT24G2ZBHLG | IC PCI SW 24LANE 24PORT 324BGA |
| IDT89HPES16NT2ZBBCG | IC PCI SW 16LANE 2PORT 484-CABGA |
| IDT89HPES24NT3ZBBXG | IC PCI SW 24LANE 3PORT 420-SBGA |
| IDT89HPES32T8ZHBXG | IC PCI SW 32LANE 8PORT 500-SBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT88P8344 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。