參數(shù)資料
型號(hào): IDT88P8342BHI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 50/98頁(yè)
文件大?。?/td> 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88P8342BHI
54
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
Theprimaryinterruptstatusregister(0x2Cinthedirectaccessedspace)has
read-only access. The interrupts for the primary interrupt status register must
be acknowledged by servicing the corresponding secondary interrupt status
registers.
MODULE_A
When active, the MODULE_A field is responsible for
allowinganinterruptintheModuleStatusRegister(secondaryinterruptregister
0x24).
0=No MODULE_A interrupt active
1=MODULE_A interrupt is active
MODULE_B
When active, the MODULE_B field is responsible for
allowing an interrupt in the module status register (secondary interrupt register
0x25).
0=No MODULE_B interrupt active
1=MODULE_B interrupt is active
SPI-43_INSERT_EN
SPI-4 ingress to SPI-3 egress insert event
interrupt enable.
0=Disable insert interrupt
1=Enable insert interrupt
PMON_EN
Performance Monitor event interrupt enable.
0=Disable PMON interrupt
1=Enable PMON interrupt
Primary interrupt status register (0x2C in the
direct accessed space)
SPI-4 When active, the SPI-4 field is responsible for allowing an interrupt
in the SPI-4 status register (secondary interrupt register 0x22).
0=No SPI-4 interrupt active
1=SPI-4 interrupt is active
SECONDARY
When active, the SECONDARY field is responsible for
allowing an interrupt in the Secondary Interrupt Status Register (secondary
interrupt register 0x2D).
0=No SECONDARY interrupt active
1=SECONDARY interrupt is active
Secondary interrupt status register (0x2D in the
direct accessed space)
Field
Bits
Length
Initial Value
MODULE_A
0
1
0
MODULE_B
1
0
Reserved
2
1
0
Reserved
3
1
0
SPI-4
4
1
0
SECONDARY
5
1
0
Reserved
7:6
2
0
TABLE 44 - PRIMARY INTERRUPT STATUS REGIS-
TER (0x2C IN THE DIRECT ACCESSED SPACE)
Field
Bits
Length
Initial Value
TIME_BASE
0
1
0
INDIRECT_ACCESS
1
0
Reserved
7:2
6
0
TABLE 45 - SECONDARY INTERRUPT STATUS
REGISTER (0x2D IN THE DIRECT ACCESSED SPACE)
The secondary interrupt status register (0x2D in the direct accessed space)
has read and write access.
Thesecondaryinterruptstatusregisterhasreadaccess,andInterruptstatus
fields are cleared by a microprocessor write cycle, where a logical one must
be written to clear the field(s) targeted.
Thesecondaryinterruptstatusregisterisasecondaryinterruptstatusregister
and can only be active if the SECONDARY_EN field is active in the primary
interrupt enable register (Direct 0x2C).
TIME_BASE
Time base expiration interrupt indication.
0=No time base event
1=Time base has expired
INDIRECT_ACCESS
Indirectaccesscompletioninterruptindication.
0=No indirect access event
1=Indirect access has completed
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