參數(shù)資料
型號(hào)： IDT88P8342BHI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 26/98頁(yè)
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8342BHI
32
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
SPI-4 ingress to SPI-3 egress flow control
The SPI-4 control information is transmitted to the adjacent device. The
adjacent device determines which LP to service next according to the status
information it receives from the IDT88P8342. The SPI-4 ingress data arrive in
bursts that are of equal length except for the last burst of a packet which may
be shorter.
The SPI-4 burst data is transferred to the per LID allocated buffer segments.
The addition of the data may cause an update of the SPI-4 status information
(starving,hungry,satisfied),andmaychangetheSPI-3STPA,DTPA,orPTPA
signals when in PHY mode.
Forthecontrolinformationtherearetwoseparatecasestoconsider:thecase
thattheSPI-3isconfiguredtoLinkmode,andthecasethattheSPI-3isconfigured
to PHY mode. Note that since the SPI-3 physical interfaces are configured
separately, the IDT88P8342 device is able to deal with the case that some of
the LP fragments are to be transmitted on a Link SPI-3 interface and some are
to be transmitted on a PHY SPI-3 interface
When in PHY mode, the data is sent according the availability of the data in
the buffer segment pool. In the Link mode an extra consideration is taken to
account – that of the fill level of the ingress FIFOs in the adjacent device.
Backpressure threshold
- Number of free segments allocated to trigger backpressure for the LP
The diagram below shows the SPI-4 to SPI-3 flow control path through the
IDT88P8342 device.
Figure 20. SPI-4 ingress to SPI-3 egress flow control
…
JTAG
uproc
LID Counters Memory
2 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
Interface
Bloc
k
Chip Counters Memory
Interface
Bloc
k
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6371 drw13a
STATUS
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